RTAX2000SL-CGS624B vs RTAX2000S-CG624PROTO Comparaison
Comparaison détaillée côte à côte de RTAX2000SL-CGS624B par Microchip Technology et RTAX2000S-CG624PROTO par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Microchip Technology
RTAX2000SL-CGS624B - 2M-Gate Rad-Tolerant FPGA, 624-CCGA | Microchip
RTAX2000SL-CGS624B ✓ ActifMicrochip Technology
RTAX2000S-CG624PROTO - 2M-Gate Rad-Tolerant FPGA CCGA-624 | Microchip
RTAX2000S-CG624PROTO ✓ ActifComparaison des spécifications
| Paramètre | RTAX2000SL-CGS624B | RTAX2000S-CG624PROTO |
|---|---|---|
| Marque | Microchip Technology | Microchip Technology |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $0,00 |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | RTAX-S Radiation-Tolerant FPGA |
| Logic Blocks (CLBs) | 21504 | — |
| Equivalent System Gates | 2000000 | — |
| ASIC Gates | 250000 | — |
| Fréquence d'horloge maximale | 350 MHz | — |
| Process Technology | 0.15 um CMOS | — |
| Tension d'alimentation | 1.5 V | [DATA_NEEDED: core and I/O supply voltage] |
| Programming Technology | Anti-fuse (one-time programmable) | — |
| Embedded Memory | Embedded SRAM with FIFO control logic | Embedded SRAM blocks (FIFO / dual-port capable) |
| Boîtier | 624-pin Ceramic Column Grid Array (CCGA) | CCGA-624 (ceramic column grid array, 624 balls) |
| Type de montage | Surface Mount | Surface Mount |
| Radiation Tolerance | Radiation-tolerant (space-flight qualified family) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | -55C to +125C |
| Number of I/Os | [DATA_NEEDED: user I/O count] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Qualification | QML per Mil Prf 38535 family (DLA cross-reference qualified program) | — |
| System Gates | — | 2,000,000 |
| Logic Cells (R-cells) | — | 21,504 |
| D-Flip-Flops (Registers) | — | 32,256 |
| Logic Architecture | — | CMOS antifuse (OTP), SEU-hardened |
| Logic Family | — | CMOS |
| Configuration | — | Live at power-up (non-volatile antifuse) |
| SEU Immunity | — | SEU rate < 10^-10 errors/bit-day (per family datasheet) |
| Prototyping Variant | — | Yes (PROTO suffix) |
| I/O Standards | — | Single-ended and differential (P/N pin pairs) |
| Design Software | — | Microsemi/Microchip Libero SoC |
| Total Ionizing Dose (TID) | — | [DATA_NEEDED: TID rating in krad(Si)] |
| Maximum I/O Count (624-ball pkg) | — | [DATA_NEEDED: user I/O count] |
| Moisture Sensitivity Level | — | [DATA_NEEDED: MSL level] |