RTAX2000SL-CGS624B vs RTAX2000S-CG624PROTO Comparação
Comparação detalhada lado a lado de RTAX2000SL-CGS624B por Microchip Technology e RTAX2000S-CG624PROTO por Microchip Technology. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Microchip Technology
RTAX2000SL-CGS624B - 2M-Gate Rad-Tolerant FPGA, 624-CCGA | Microchip
RTAX2000SL-CGS624B ✓ AtivoMicrochip Technology
RTAX2000S-CG624PROTO - 2M-Gate Rad-Tolerant FPGA CCGA-624 | Microchip
RTAX2000S-CG624PROTO ✓ AtivoComparação de especificações
| Parâmetro | RTAX2000SL-CGS624B | RTAX2000S-CG624PROTO |
|---|---|---|
| Marca | Microchip Technology | Microchip Technology |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Ativo | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $0,00 | $0,00 |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | RTAX-S Radiation-Tolerant FPGA |
| Logic Blocks (CLBs) | 21504 | — |
| Equivalent System Gates | 2000000 | — |
| ASIC Gates | 250000 | — |
| Frequência máxima de clock | 350 MHz | — |
| Process Technology | 0.15 um CMOS | — |
| Tensão de alimentação | 1.5 V | [DATA_NEEDED: core and I/O supply voltage] |
| Programming Technology | Anti-fuse (one-time programmable) | — |
| Embedded Memory | Embedded SRAM with FIFO control logic | Embedded SRAM blocks (FIFO / dual-port capable) |
| Encapsulamento | 624-pin Ceramic Column Grid Array (CCGA) | CCGA-624 (ceramic column grid array, 624 balls) |
| Tipo de montagem | Surface Mount | Surface Mount |
| Radiation Tolerance | Radiation-tolerant (space-flight qualified family) | — |
| Temperatura de operação | [DATA_NEEDED: operating temperature range] | -55C to +125C |
| Number of I/Os | [DATA_NEEDED: user I/O count] | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Qualification | QML per Mil Prf 38535 family (DLA cross-reference qualified program) | — |
| System Gates | — | 2,000,000 |
| Logic Cells (R-cells) | — | 21,504 |
| D-Flip-Flops (Registers) | — | 32,256 |
| Logic Architecture | — | CMOS antifuse (OTP), SEU-hardened |
| Logic Family | — | CMOS |
| Configuration | — | Live at power-up (non-volatile antifuse) |
| SEU Immunity | — | SEU rate < 10^-10 errors/bit-day (per family datasheet) |
| Prototyping Variant | — | Yes (PROTO suffix) |
| I/O Standards | — | Single-ended and differential (P/N pin pairs) |
| Design Software | — | Microsemi/Microchip Libero SoC |
| Total Ionizing Dose (TID) | — | [DATA_NEEDED: TID rating in krad(Si)] |
| Maximum I/O Count (624-ball pkg) | — | [DATA_NEEDED: user I/O count] |
| Moisture Sensitivity Level | — | [DATA_NEEDED: MSL level] |