RTAX250SL-CQ208V vs RTAX250SL-1CQ208PROTO Comparaison
Comparaison détaillée côte à côte de RTAX250SL-CQ208V par Microsemi et RTAX250SL-1CQ208PROTO par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Microchip Technology
RTAX250SL-1CQ208PROTO - 250k-Gate Rad-Tolerant FPGA | Microchip
RTAX250SL-1CQ208PROTO ✓ ActifComparaison des spécifications
| Paramètre | RTAX250SL-CQ208V | RTAX250SL-1CQ208PROTO |
|---|---|---|
| Marque | Microsemi | Microchip Technology |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1,00 | $0,00 |
| Programmable Logic Type | Radiation-Tolerant FPGA (antifuse, live at power-up) | — |
| System Gates | 250000 gates | — |
| Logic Cells | 4224 | 4224 |
| CLBs | 2816 | — |
| Process Technology | 0.15 um CMOS | — |
| Core Supply Voltage | 1.5 V nominal | — |
| Température de fonctionnement | -55C to +125C | [DATA_NEEDED: operating temperature range] |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| Maximum Frequency (family) | 649 MHz | — |
| Boîtier | 208-Pin CQFP (ceramic quad flat pack) | CQFP-208 (CQ208) ceramic quad flat pack |
| Radiation Qualification Suffix | V (radiation qualified, space flight grade) | — |
| Configuration | Single-chip, live-at-power-up (no external boot device) | Live at power-up (antifuse, no boot device) |
| Clocking | Segmentable clocks, chip-wide highway routing | — |
| Special Logic | Carry logic for arithmetic; SEU-hardened flip-flops (SL variant) | — |
| Type de montage | Surface Mount | Surface Mount |
| Family | RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs | RTAX-S/SL Radiation-Tolerant FPGAs |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Equivalent System Gates | — | 250,000 |
| Configurable Logic Blocks (CLBs) | — | 2816 |
| Combinatorial CLB Delay | — | 0.93 ns maximum (minimum -1 speed grade per source data) |
| Speed Grade | — | -1 |
| Technology | — | CMOS antifuse (one-time programmable) |
| Total Ionizing Dose Tolerance | — | Enhanced (SL variant) |
| Clock Features | — | Segmentable chip-wide clocks |
| Application Grade | — | Space-flight (radiation-tolerant), PROTO screening |
| Tension d'alimentation | — | [DATA_NEEDED: core supply voltage] |