RTAX250SL-LG624V vs RTAX250SL-1CG624E Comparaison
Comparaison détaillée côte à côte de RTAX250SL-LG624V par Microchip Technology et RTAX250SL-1CG624E par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Microchip Technology
RTAX250SL-LG624V - 250K-Gate Rad-Tolerant FPGA | Microchip
RTAX250SL-LG624V ✓ ActifMicrochip Technology
RTAX250SL-1CG624E - 250K Gate Rad-Tolerant FPGA, CCGA-624 | Microchip
RTAX250SL-1CG624E ✓ ActifComparaison des spécifications
| Paramètre | RTAX250SL-LG624V | RTAX250SL-1CG624E |
|---|---|---|
| Marque | Microchip Technology | Microchip Technology |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 620,00 | $1,00 |
| Equivalent System Gates | 250000 gates | 250,000 gates |
| Configurable Logic Blocks (CLBs) | 2816 | 2816 |
| Logic Cells | 4224 | 4224 |
| Process Technology | 0.15 um CMOS | 0.15 um CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V (1.425 V to 1.575 V) |
| User I/O | 248 | 248 inputs / 248 outputs |
| Boîtier | 624-pin LGA (LG624) | 624-ball Ceramic Column Grid Array (CCGA-624) |
| Family | RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs | — |
| Program Technology | Anti-fuse, one-time programmable | — |
| Configuration | Live at power-up, single chip | Live-at-power-up, true single-chip operation |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| Clocking | Segmentable clocks, chip-wide highway routing | — |
| Radiation Tolerance | Radiation-tolerant, SEU-mitigated (SL variant) | SEU-immune to specified LET threshold; SEU rate < 10-10 errors/bit-day |
| Type de montage | Surface Mount | Surface Mount (ceramic column grid array) |
| Statut RoHS | [DATA_NEEDED: RoHS Status] | [DATA_NEEDED: RoHS status] |
| Température de fonctionnement | [DATA_NEEDED: Operating Temperature] | -55C to +125C |
| Maximum Combinatorial Delay (CLB) | — | 0.93 ns |
| Maximum System Frequency | — | 649 MHz |
| Logic Family | — | CMOS |
| SEU Mitigation | — | SEU-hardened registers (no external TMR required) |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O bank voltage] |