XC3090L-6TQG176C vs XC3090L-6TQG176I Comparaison
Comparaison détaillée côte à côte de XC3090L-6TQG176C par Xilinx et XC3090L-6TQG176I par Xilinx. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | XC3090L-6TQG176C | XC3090L-6TQG176I |
|---|---|---|
| Marque | Xilinx | Xilinx |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $63,00 | $21,40 |
| Family | XC3000L Low-Voltage Logic Cell Array | XC3000L Low Voltage Logic Cell Array |
| Series | XC3000L | — |
| Device | XC3090L | — |
| Speed Grade | -6 (6 ns tpd) | -6 (approximately 6 ns combinatorial delay) |
| User I/O Count | 138 | — |
| Boîtier | TQG176 (Thin Quad Gull-Wing, 176 pins) | TQG176 (176-pin Thin Quad Flat Pack) |
| Tension d'alimentation | 3.3 V | — |
| Combinatorial Logic Delay (tpd) | 6 ns | — |
| Configuration Memory | SRAM (volatile, in-system programmable) | SRAM (volatile, requires external configuration PROM) |
| Température de fonctionnement | Commercial (0C to +70C) | — |
| Type de montage | Surface Mount | Surface Mount |
| Family Differentiator | Low-voltage 3.3V core vs 5.0V XC3000A | — |
| Compatible Programming Tools | Xilinx XChecker, JTAG boundary-scan, PROM-based serial configuration | — |
| Statut RoHS | unknown (legacy family, pre-dates RoHS documentation conventions) | [DATA_NEEDED: RoHS compliance] |
| Lead Free | unknown | — |
| Pinout Type | Perimeter I/O ring with user I/O and dedicated configuration pins | — |
| Product Type | — | SRAM-based FPGA |
| Usable Gates | — | 900 |
| Logic Cells (CLBs) | — | [DATA_NEEDED: CLB count] |
| Supply Voltage (VCC) | — | 3.3 V |
| Operating Temperature Grade | — | Industrial (-40C to +85C) |
| Configuration Modes | — | 5 (Master Serial, Slave Serial, Master Parallel, Slave Parallel, Peripheral) |
| Boundary Scan | — | JTAG IEEE 1149.1 |
| Readback | — | Supported |
| Process Technology | — | CMOS, 5 V tolerant I/O on selected variants |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |