XC3090L-7TQ176C vs XC3090L-6TQG176C Comparaison
Comparaison détaillée côte à côte de XC3090L-7TQ176C par Xilinx et XC3090L-6TQG176C par Xilinx. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | XC3090L-7TQ176C | XC3090L-6TQG176C |
|---|---|---|
| Marque | Xilinx | Xilinx |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $47,50 | $63,00 |
| Family | XC3000L Low-Voltage Logic Cell Array | XC3000L Low-Voltage Logic Cell Array |
| Series | XC3000L | XC3000L |
| Logic Cells | [DATA_NEEDED: logic cell count] | — |
| Gates | [DATA_NEEDED: equivalent gate count] | — |
| Configurable Logic Blocks (CLBs) | [DATA_NEEDED: CLB count] | — |
| User I/O | [DATA_NEEDED: user I/O count] | — |
| Speed Grade | -7 | -6 (6 ns tpd) |
| Core Voltage | 3.3 V (low-voltage family) | — |
| Boîtier | TQFP-176 | TQG176 (Thin Quad Gull-Wing, 176 pins) |
| Température de fonctionnement | 0 °C to +85 °C (Commercial, "C" suffix) | Commercial (0C to +70C) |
| Configuration Memory | SRAM (volatile, external config required) | SRAM (volatile, in-system programmable) |
| Process Technology | [DATA_NEEDED: process node] | — |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS status] | unknown (legacy family, pre-dates RoHS documentation conventions) |
| Lead Free | [DATA_NEEDED: lead free status] | unknown |
| Programming Interface | Xilinx XACTstep / Foundation toolchain | — |
| Device | — | XC3090L |
| User I/O Count | — | 138 |
| Tension d'alimentation | — | 3.3 V |
| Combinatorial Logic Delay (tpd) | — | 6 ns |
| Family Differentiator | — | Low-voltage 3.3V core vs 5.0V XC3000A |
| Compatible Programming Tools | — | Xilinx XChecker, JTAG boundary-scan, PROM-based serial configuration |
| Pinout Type | — | Perimeter I/O ring with user I/O and dedicated configuration pins |