XC3090L-7TQ176C vs XC3090L-6TQG176I Comparaison
Comparaison détaillée côte à côte de XC3090L-7TQ176C par Xilinx et XC3090L-6TQG176I par Xilinx. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | XC3090L-7TQ176C | XC3090L-6TQG176I |
|---|---|---|
| Marque | Xilinx | Xilinx |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $47,50 | $21,40 |
| Family | XC3000L Low-Voltage Logic Cell Array | XC3000L Low Voltage Logic Cell Array |
| Series | XC3000L | — |
| Logic Cells | [DATA_NEEDED: logic cell count] | — |
| Gates | [DATA_NEEDED: equivalent gate count] | — |
| Configurable Logic Blocks (CLBs) | [DATA_NEEDED: CLB count] | — |
| User I/O | [DATA_NEEDED: user I/O count] | — |
| Speed Grade | -7 | -6 (approximately 6 ns combinatorial delay) |
| Core Voltage | 3.3 V (low-voltage family) | — |
| Boîtier | TQFP-176 | TQG176 (176-pin Thin Quad Flat Pack) |
| Température de fonctionnement | 0 °C to +85 °C (Commercial, "C" suffix) | — |
| Configuration Memory | SRAM (volatile, external config required) | SRAM (volatile, requires external configuration PROM) |
| Process Technology | [DATA_NEEDED: process node] | CMOS, 5 V tolerant I/O on selected variants |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Lead Free | [DATA_NEEDED: lead free status] | — |
| Programming Interface | Xilinx XACTstep / Foundation toolchain | — |
| Product Type | — | SRAM-based FPGA |
| Usable Gates | — | 900 |
| Logic Cells (CLBs) | — | [DATA_NEEDED: CLB count] |
| Supply Voltage (VCC) | — | 3.3 V |
| Operating Temperature Grade | — | Industrial (-40C to +85C) |
| Configuration Modes | — | 5 (Master Serial, Slave Serial, Master Parallel, Slave Parallel, Peripheral) |
| Boundary Scan | — | JTAG IEEE 1149.1 |
| Readback | — | Supported |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |