XC3090L-7TQ176C vs XC3090L-6TQG176I Comparación
Comparación detallada lado a lado de XC3090L-7TQ176C por Xilinx y XC3090L-6TQG176I por Xilinx. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | XC3090L-7TQ176C | XC3090L-6TQG176I |
|---|---|---|
| Marca | Xilinx | Xilinx |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $47,50 | $21,40 |
| Family | XC3000L Low-Voltage Logic Cell Array | XC3000L Low Voltage Logic Cell Array |
| Series | XC3000L | — |
| Logic Cells | [DATA_NEEDED: logic cell count] | — |
| Gates | [DATA_NEEDED: equivalent gate count] | — |
| Configurable Logic Blocks (CLBs) | [DATA_NEEDED: CLB count] | — |
| User I/O | [DATA_NEEDED: user I/O count] | — |
| Speed Grade | -7 | -6 (approximately 6 ns combinatorial delay) |
| Core Voltage | 3.3 V (low-voltage family) | — |
| Encapsulado | TQFP-176 | TQG176 (176-pin Thin Quad Flat Pack) |
| Temperatura de funcionamiento | 0 °C to +85 °C (Commercial, "C" suffix) | — |
| Configuration Memory | SRAM (volatile, external config required) | SRAM (volatile, requires external configuration PROM) |
| Process Technology | [DATA_NEEDED: process node] | CMOS, 5 V tolerant I/O on selected variants |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Lead Free | [DATA_NEEDED: lead free status] | — |
| Programming Interface | Xilinx XACTstep / Foundation toolchain | — |
| Product Type | — | SRAM-based FPGA |
| Usable Gates | — | 900 |
| Logic Cells (CLBs) | — | [DATA_NEEDED: CLB count] |
| Supply Voltage (VCC) | — | 3.3 V |
| Operating Temperature Grade | — | Industrial (-40C to +85C) |
| Configuration Modes | — | 5 (Master Serial, Slave Serial, Master Parallel, Slave Parallel, Peripheral) |
| Boundary Scan | — | JTAG IEEE 1149.1 |
| Readback | — | Supported |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |