XC3090L-7TQ176C vs XC3090L-7TQG176C Comparaison
Comparaison détaillée côte à côte de XC3090L-7TQ176C par Xilinx et XC3090L-7TQG176C par Xilinx. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | XC3090L-7TQ176C | XC3090L-7TQG176C |
|---|---|---|
| Marque | Xilinx | Xilinx |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $47,50 | $21,20 |
| Family | XC3000L Low-Voltage Logic Cell Array | XC3000L |
| Series | XC3000L | — |
| Logic Cells | [DATA_NEEDED: logic cell count] | — |
| Gates | [DATA_NEEDED: equivalent gate count] | — |
| Configurable Logic Blocks (CLBs) | [DATA_NEEDED: CLB count] | — |
| User I/O | [DATA_NEEDED: user I/O count] | — |
| Speed Grade | -7 | — |
| Core Voltage | 3.3 V (low-voltage family) | — |
| Boîtier | TQFP-176 | 176-pin TQFP (TQG176), 1.4 mm height, surface-mount |
| Température de fonctionnement | 0 °C to +85 °C (Commercial, "C" suffix) | — |
| Configuration Memory | SRAM (volatile, external config required) | SRAM (volatile, requires external PROM) |
| Process Technology | [DATA_NEEDED: process node] | 0.8 micron CMOS |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Lead Free | [DATA_NEEDED: lead free status] | — |
| Programming Interface | Xilinx XACTstep / Foundation toolchain | — |
| Device | — | XC3090L |
| Logic Cells / CLBs | — | 100 CLBs (320 F-FFs) |
| Usable Gates | — | 5,000 (typical, up to 9,000 peak) |
| User I/O Count | — | 144 (maximum, TQG176) |
| Supply Voltage (Core) | — | 3.0 V to 3.6 V |
| Supply Voltage (I/O VCCO) | — | 3.0 V to 3.6 V |
| Logic Cell Toggle Delay | — | approximately 1.3 to 1.5 ns (-7 speed grade) |
| Plage de température de fonctionnement | — | 0C to +85C (C suffix, commercial) |
| Configuration Mode | — | Serial (master/slave) and JTAG (IEEE 1149.1) |
| Niveau MSL | — | 3 (168 hours) [DATA_NEEDED: confirm per package marking] |
| Lead-Free / Lead Content | — | [DATA_NEEDED] |
| Configuration Clock Source | — | Internal oscillator amplifier or external pin |
| Output Drive (per I/O) | — | 8 mA source / 24 mA sink (typical, datasheet TBD by speed grade) |