XC6SLX16-2FTG256I vs XC6SLX16-2FTG256C Comparaison
Comparaison détaillée côte à côte de XC6SLX16-2FTG256I par AMD et XC6SLX16-2FTG256C par AMD. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | XC6SLX16-2FTG256I | XC6SLX16-2FTG256C |
|---|---|---|
| Marque | AMD | AMD |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | NRND |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| FPGA Family | Spartan-6 LX | — |
| Logic Cells | 14,579 cells | 14,579 |
| Configurable Logic Blocks | 1,139 CLBs | — |
| Adaptive Logic Modules | 2,278 ALMs | — |
| User I/Os | 186 I/Os | — |
| Internal Frequency | 667 MHz | — |
| Additional Stated Frequency | 375 MHz | — |
| Core Supply Voltage | 1.14 V to 1.26 V | — |
| Process Technology | CMOS | — |
| Boîtier | FTGBGA-256 | 256-ball Fine-Pitch Thin BGA (FTG256), 17×17 mm, 1.0 mm pitch |
| Package Body Size | 17 mm x 17 mm | — |
| Package Ball Pitch | 1.00 mm | — |
| Lead-Free Status | Lead free | — |
| Température de fonctionnement | 0°C to 85°C | 0 °C to +85 °C (Commercial) |
| Speed Grade | -2 | -2 |
| Embedded Resources | DCM, PLL, block RAM, and DSP | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | — |
| REACH Status | [DATA_NEEDED: REACH compliance] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Family | — | Spartan-6 LX |
| Configurable Logic Blocks (CLBs) | — | 1,139 |
| Slices | — | 2,278 |
| Block RAM Bits | — | 589,824 bits |
| Block RAM Blocks (18 Kb) | — | 32 |
| DSP Slices (18×18 multipliers) | — | 32 |
| Maximum User I/Os | — | 186 |
| Maximum Single-Ended I/O Banks | — | 4 |
| Process Node | — | 45 nm CMOS, 9-metal layer |
| Supply Voltage (Core) | — | 1.2 V nominal |
| Type de montage | — | Surface Mount |
| Lead-Free / RoHS | — | Yes (compliant) |
| Configuration Modes | — | JTAG, SPI (x1/x2/x4), BPI (x8/x16), Slave-Parallel |
| Clock Management Tiles (CMTs) | — | 2 (each with PLL + MMCM) |
| PCIe Support | — | Soft IP only (no integrated PCIe hard cores) |