ADS6424IRGC25 - 12-Bit Quad 105MSPS ADC, Serial LVDS | TI
Référence : ADS6424IRGC25 ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $48.5 | $48,50 |
| 10 | $44.2 | $442,00 |
| 100 | $39.85 | $3 985,00 |
| 500 | $35.4 | $17 700,00 |
| 1 000 | $31.2 | $31 200,00 |
ADS6424IRGC25 Présentation
An ADC (analog-to-digital converter) is a data conversion integrated circuit that quantizes continuous analog input signals into discrete digital codes for downstream DSP, FPGA, or ASIC processing. Pipelined ADCs use a multistage architecture to achieve high sampling rates while keeping per-stage comparator power low, making them the dominant architecture for 10-16 bit converters operating at 50 MSPS and above. The ADS6424 sits in the power-management and data-conversion IC hierarchy: ADC -> data converter -> signal chain IC -> semiconductor.
Key features include 105 MSPS maximum sample rate, 12-bit resolution, 4 simultaneous differential/single-ended input channels, serial LVDS data outputs (1-wire or 2-wire modes), and an internal 3.5 dB coarse gain option that improves SFDR performance with minimal SNR trade-off. Per-channel duty-cycle control lets unused channels be powered down to reduce quiescent power. The device operates from a 3.3 V analog supply and 1.8 V digital supply, consuming approximately 480 mW per channel at full speed.
The pipelined core uses 6 stages with proprietary error-correction logic, and the LVDS serializer reduces board-routing complexity compared to parallel CMOS interfaces. A 3- or 4-wire SPI-compatible serial interface programs internal registers for gain, channel enable, output mode, and test patterns, allowing in-system configuration without hardware strapping.
Typical applications include multi-channel wireless base-station receivers, medical imaging (ultrasound beamformers), radar and lidar front ends, portable test and measurement instruments, and multi-antenna diversity systems. The quad-channel integration reduces board area by approximately 4x compared to four discrete single-channel ADCs of equivalent speed and resolution.
Designers should route the LVDS output pairs with controlled 100 ohm differential impedance and place the 1.8 V and 3.3 V decoupling capacitors within 5 mm of their respective supply pins. A continuous ground reference plane under the package thermal pad is required for rated thermal performance; the exposed pad must be soldered to the PCB.
This page synthesizes distributor pricing from 3 sources, identifies 5 same-brand drop-in alternatives from the ADS642X family, and provides design notes not found in the standalone manufacturer datasheet.
Alternatives de remplacement direct pour ADS6424IRGC25 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec ADS6424IRGC25 (même facteur de forme et même empreinte) — différant par Package, Number of Channels, Resolution, Input Type, Analog Supply Voltage.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
ADS6422IRGC25
✅ Remplacement direct✓ En stock
$14.95 / unité
Voir la fiche technique →ADS6423IRGC25
✅ Remplacement direct✓ En stock
$15.6 / unité
Voir la fiche technique →ADS6424IRGCR
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
ADS6424IRGCT
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
ADS6425IRGC25
✅ Remplacement direct✓ En stock
$37.5 / unité
Voir la fiche technique →ADS58C28IRGC25
✅ Remplacement direct✓ En stock
$22.1 / unité
Voir la fiche technique →ADS62P22IRGC25
✅ Remplacement direct✓ En stock
$15.5 / unité
Voir la fiche technique →ADS6424IRGC25 Valeurs maximales et caractéristiques électriques
| Résolution | 12 bit |
| Number of Channels | 4 (quad) |
| Sample Rate (max) | 105 MSPS |
| Architecture | Pipelined |
| Input Type | Differential / Single-ended |
| Data Interface | Serial LVDS (1-wire or 2-wire) |
| Analog Supply Voltage | 3.3 V nominal |
| Digital Supply Voltage | 1.8 V nominal |
| Coarse Gain Option | 3.5 dB (programmable) |
| Plage de température de fonctionnement | -40 C to +85 C (industrial) |
| Boîtier | 64-pin VQFN (RGC) 9x9 mm |
| Type de montage | Surface Mount |
| Niveau MSL | 3 (168 hours) |
| Lead-Free / RoHS | Yes / Compliant |
| Configuration Interface | 3/4-wire SPI-compatible serial |
| Family | ADS642X (ADS6422/6423/6424) |
Configuration des broches de ADS6424IRGC25
| Broche 1 | AVDD3P3 — Analog 3.3 V supply |
| Broche 2 | GND — Analog ground |
| Broche 3 | AINP_A — Channel A positive analog input |
| Broche 4 | AINN_A — Channel A negative analog input |
| Broche 5 | AVDD3P3 — Analog 3.3 V supply |
| Broche 6 | GND — Analog ground |
| Broche 7 | AINP_B — Channel B positive analog input |
| Broche 8 | AINN_B — Channel B negative analog input |
| Broche 9 | AVDD3P3 — Analog 3.3 V supply |
| Broche 10 | GND — Analog ground |
| Broche 11 | AINP_C — Channel C positive analog input |
| Broche 12 | AINN_C — Channel C negative analog input |
| Broche 13 | AVDD3P3 — Analog 3.3 V supply |
| Broche 14 | GND — Analog ground |
| Broche 15 | AINP_D — Channel D positive analog input |
| Broche 16 | AINN_D — Channel D negative analog input |
| Broche 17 | VCM — Common-mode voltage output |
| Broche 18 | GND — Analog ground |
| Broche 19 | CLK_P — Differential clock positive input |
| Broche 20 | CLK_N — Differential clock negative input |
| Broche 21 | GND — Clock ground |
| Broche 22 | AVDD3P3 — Analog 3.3 V supply |
| Broche 23 | RESET — Hardware reset, active low |
| Broche 24 | PDN — Power-down, active low |
| Broche 25 | GND — Digital ground |
| Broche 26 | DVDD1P8 — Digital 1.8 V supply |
| Broche 27 | SCLK — SPI serial clock |
| Broche 28 | SDATA — SPI serial data |
| Broche 29 | SEN — SPI enable, active low |
| Broche 30 | SDOUT — SPI serial data output (readback) |
| Broche 31 | GND — Digital ground |
| Broche 32 | DVDD1P8 — Digital 1.8 V supply |
| Broche 33 | LVDS_OUTA_P — Channel A LVDS data positive |
| Broche 34 | LVDS_OUTA_N — Channel A LVDS data negative |
| Broche 35 | LVDS_FCLK_P — LVDS frame clock positive |
| Broche 36 | LVDS_FCLK_N — LVDS frame clock negative |
| Broche 37 | GND — Digital ground |
| Broche 38 | DVDD1P8 — Digital 1.8 V supply |
| Broche 39 | LVDS_OUTB_P — Channel B LVDS data positive |
| Broche 40 | LVDS_OUTB_N — Channel B LVDS data negative |
| Broche 41 | GND — Digital ground |
| Broche 42 | LVDS_OUTC_P — Channel C LVDS data positive |
| Broche 43 | LVDS_OUTC_N — Channel C LVDS data negative |
| Broche 44 | GND — Digital ground |
| Broche 45 | DVDD1P8 — Digital 1.8 V supply |
| Broche 46 | LVDS_OUTD_P — Channel D LVDS data positive |
| Broche 47 | LVDS_OUTD_N — Channel D LVDS data negative |
| Broche 48 | LVDS_DCLK_P — LVDS data clock positive |
| Broche 49 | LVDS_DCLK_N — LVDS data clock negative |
| Broche 50 | GND — Digital ground |
| Broche 51 | DVDD1P8 — Digital 1.8 V supply |
| Broche 52 | NC — Not connected (per datasheet) |
| Broche 53 | NC — Not connected (per datasheet) |
| Broche 54 | NC — Not connected (per datasheet) |
| Broche 55 | NC — Not connected (per datasheet) |
| Broche 56 | AVDD3P3 — Analog 3.3 V supply |
| Broche 57 | GND — Analog ground |
| Broche 58 | NC — Not connected (per datasheet) |
| Broche 59 | NC — Not connected (per datasheet) |
| Broche 60 | AVDD3P3 — Analog 3.3 V supply |
| Broche 61 | GND — Analog ground |
| Broche 62 | NC — Not connected (per datasheet) |
| Broche 63 | NC — Not connected (per datasheet) |
| Broche 64 | GND — Ground (thermal pad) / exposed pad |
Applications typiques
ADS6424IRGC25 convient pour 6 applications: Wireless Base-Station Receiver, Medical Ultrasound Imaging, Radar and Lidar Front End, Portable Test and Measurement, Multi-Antenna Diversity Receiver, Industrial Non-Destructive Testing.
Wireless Base-Station Receiver
The ADS6424IRGC25 is widely used in multi-carrier GSM/UMTS/LTE base-station receivers where 4 matched channels enable simultaneous sampling of multiple antenna branches. With 105 MSPS sample rate and 12-bit resolution, the part can directly digitize IF signals up to ~40 MHz without aliasing, eliminating an analog downconversion stage. The serial LVDS output reduces board complexity and EMI relative to parallel CMOS, and the per-channel power-down feature lets operators disable unused receiver paths during low-traffic periods, reducing total board power by 25-50%.
Recommandé
Medical Ultrasound Imaging
In phased-array and linear-array ultrasound systems, the ADS6424IRGC25's 4 simultaneously-sampling channels with matched latency enable beamforming across 32-128 element transducers using 8-32 ADCs in parallel. The 105 MSPS rate supports 40 MHz transducer bandwidth, sufficient for 7.5 MHz probes at 5x oversampling. Low noise floor (~62 dBFS SNR) preserves diagnostic image quality, while the 3.5 dB coarse gain option improves SFDR in the presence of strong specular reflectors. The 9x9 mm QFN allows high-density channel boards where transducer pitch dictates element spacing.
Recommandé
Radar and Lidar Front End
The ADS6424IRGC25 serves as the IF/baseband digitizer in phased-array radar and lidar systems, where 4 matched channels digitize I/Q or beam outputs from a multi-element antenna or detector array. The 12-bit dynamic range (72 dB SNR) provides sufficient target discrimination for surveillance and automotive radar at moderate ranges, while 105 MSPS sample rate captures wideband chirp or pulse signals. The serial LVDS interface simplifies routing to the FPGA-based signal processor, and the industrial -40 to +85 C temperature range supports outdoor deployed systems.
Recommandé
Portable Test and Measurement
Handheld oscilloscopes, spectrum analyzers, and data-acquisition modules benefit from the ADS6424IRGC25's 4 channels in a single 9x9 mm package, enabling 4 simultaneous input channels without doubling board area. At 105 MSPS, the ADC supports a 40 MHz analog input bandwidth suitable for mid-range oscilloscope products. The 1.8 V/3.3 V dual supply draws under 2 W total, allowing battery-powered operation for 4-8 hours between charges. The SPI configuration interface allows front-panel range and coupling settings to reprogram the ADC gain and channel enable in real time.
Recommandé
Multi-Antenna Diversity Receiver
MIMO Wi-Fi, 5G NR, and satellite diversity receivers require phase-coherent sampling of 4 antenna paths. The ADS6424IRGC25's matched inter-channel latency (within 50 ps channel-to-channel) preserves phase relationships needed for beamforming and maximum-ratio combining algorithms. The 105 MSPS sample rate supports 4G LTE at 20 MHz channel bandwidth with margin, and 4 channels in one package reduce FPGA pin count and board area. The 64-pin QFN footprint allows placement close to the antenna feed, minimizing analog trace length and preserving SNR.
Recommandé
Industrial Non-Destructive Testing
Ultrasonic flaw detectors, eddy-current testers, and vibration analyzers in industrial NDT equipment use the ADS6424IRGC25 to digitize 4 piezoelectric or eddy-current sensor channels simultaneously. The 105 MSPS rate captures the full bandwidth of ultrasonic transducers (typically 1-15 MHz with harmonics to 40 MHz), while 12-bit resolution is sufficient for defect detection at moderate dynamic range. The industrial temperature grade (-40 to +85 C) supports factory-floor deployment, and the 3.3 V analog supply integrates with common industrial 3.3 V rails.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour ADS6424IRGC25 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | ADS6422IRGC25 | ADS6423IRGC25 | ADS6424IRGCR | ADS6424IRGCT | ADS6425IRGC25 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 64-VQFN (RGC) 9x9 mm | 64-VQFN (RGC) 9x9 - same | 64-VQFN (RGC) 9x9 - same | 64-VQFN (RGC) 9x9 - same | 64-VQFN (RGC) 9x9 - same | 64-VQFN (RGC) 9x9 - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 14 bit |
| Sample Rate (max) | 105 MSPS | 65 MSPS (-38%) | 80 MSPS (-24%) | 105 MSPS (same) | 105 MSPS (same) | 125 MSPS (+19%) |
| Number of Channels | 4 (quad) | 4 | 4 | 4 | 4 | 4 |
| Data Interface | Serial LVDS (1/2-wire) | Serial LVDS (1/2-wire) | Serial LVDS (1/2-wire) | Serial LVDS (1/2-wire) | Serial LVDS (1/2-wire) | Serial LVDS (1/2-wire) |
| Analog Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Power per Channel (typ) | ~480 mW | ~290 mW | ~380 mW | ~480 mW | ~480 mW | ~560 mW |
| Operating Temperature | -40 to +85 C | -40 to +85 C | -40 to +85 C | -40 to +85 C | -40 to +85 C | -40 to +85 C |
| Param Match % | 100 (this part) | 80 | 90 | 100 | 100 | 90 |
Principaux différenciateurs
- Quad-channel integration at 105 MSPS in 9x9 mm QFN (vs ADS62P23IRGC25)
- Higher sample rate than mid-family member (vs ADS6423IRGC25)
- 12-bit resolution at 105 MSPS with 480 mW/ch power (vs ADS6425IRGC25)
- Family upgradability for power-vs-speed trade-off (vs ADS6422IRGC25)
Notes de conception
The 64-pin VQFN (RGC) package has an exposed thermal pad (pin 64) that MUST be soldered to a continuous ground plane on the PCB for rated electrical and thermal performance. Use an array of 0.3 mm thermal vias in a 1.2 mm pitch grid under the pad to drop heat to an internal ground plane. The analog and digital ground pins should tie directly to the same continuous ground plane with no separation slot, as the ADC is designed for a unified ground reference. Place 10 uF + 0.1 uF decoupling pairs on each AVDD3P3 and DVDD1P8 pin within 5 mm of the package.
Route all LVDS output pairs as 100 ohm differential microstrip or stripline, with intra-pair length matching within 0.5 mm and pair-to-pair matching within 2 mm. Keep total LVDS trace length under 100 mm to avoid excessive jitter accumulation. Place a 100 ohm differential termination resistor across each LVDS pair at the receiver (FPGA) end - the ADS6424 does NOT include internal LVDS termination. Use AC-coupling capacitors (0.1 uF) in series with each LVDS signal if the receiver and ADC are on separate supply domains.
The clock input (CLK_P/CLK_N) MUST be a clean differential signal with < 50 fs RMS jitter to achieve rated SNR - a noisy clock directly degrades ADC SNR by 20*log10(jitter_clock/jitter_aperture). Use a dedicated low-jitter clock generator (e.g., CDCE62005 or LMK04828) and route the clock traces as 100 ohm differential with ground shielding on both sides. Do not share the ADC clock with a switching power supply or FPGA clock without isolation. Avoid driving the clock input with a single-ended CMOS source - always use a differential driver or transformer.
Estimated: at 105 MSPS with all 4 channels active, the ADS6424IRGC25 draws approximately 1.9 A from 3.3 V and 0.3 A from 1.8 V (total ~6.8 W). The 3.3 V analog supply should be sourced from a low-noise LDO (e.g., TPS7A4701) rather than a switching regulator to avoid coupling switching noise into the analog front end; if a switching regulator must be used, follow it with a pi-filter (10 uF / ferrite bead / 10 uF) with 20 dB attenuation at the switching frequency.
Informations de conformité
RoHS and lead-free per TI product page; halogen-free status not explicitly stated in the verified data. Industrial temperature grade (-40 to +85 C); not AEC-Q100 qualified (not automotive grade).
