ADS6425IRGC25 - Quad 12-Bit 125 MSPS Serial LVDS ADC | Texas Instruments
Référence : ADS6425IRGC25 ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $56.4 | $56,40 |
| 10 | $50.76 | $507,60 |
| 100 | $45.12 | $4 512,00 |
| 500 | $41 | $20 500,00 |
| 1 000 | $37.5 | $37 500,00 |
ADS6425IRGC25 Présentation
Background Knowledge: An ADC (analog-to-digital converter) is a data converter that translates continuous analog signals into discrete digital codes. Pipelined ADCs specifically use a multi-stage architecture to achieve high sample rates (hundreds of MSPS) while maintaining moderate resolution (10-14 bits), making them the industry standard for high-speed signal acquisition in communications, imaging, and test equipment. Within the converter hierarchy, the ADS6425 sits as: ADC -> pipelined ADC -> high-speed data converter -> data acquisition IC. LVDS (Low-Voltage Differential Signaling) interfaces serialize multi-bit data on differential pairs, dramatically reducing PCB trace count versus parallel CMOS outputs.
Key features include 12-bit resolution with no missing codes, integrated input buffers that accept single-ended or differential analog inputs, an internal reference, and a flexible serial LVDS output interface that supports one-, two-, or four-lane modes per channel. The device operates from a single 3.3 V analog supply and a 1.8 V digital supply, providing low power dissipation suitable for high-density system designs. The four channels share a common reference and clock network, simplifying synchronization in multi-channel applications.
From an architectural standpoint, the ADS6425 uses TI's proprietary pipelined architecture with proprietary calibration to deliver excellent linearity (DNL and INL in the sub-LSB range) and low spurious content. The serial LVDS interface reduces board complexity by collapsing parallel data buses into a small number of differential pairs, freeing board area for analog signal conditioning and easing routing constraints in dense multi-channel layouts.
Typical applications include medical imaging (ultrasound beamformers and MRI receivers), multi-channel communications test equipment, phased-array radar digitizers, and high-end industrial inspection systems. Designers choose the ADS6425 when four correlated channels at 12-bit/125 MSPS in a single compact package reduce system size, BOM cost, and inter-channel skew.
Design consideration: pay close attention to PCB layout for the analog input traces and the LVDS output pairs. Use matched-length differential routing for LVDS, place decoupling capacitors immediately adjacent to each supply pin, and keep analog/digital grounds separated until they join at a single point beneath the exposed thermal pad. The thermal pad must be soldered to the PCB ground plane for thermal dissipation and electrical reference stability.
This page synthesizes distributor pricing, verified drop-in alternatives within the same VQFN-64 footprint, and practical PCB thermal notes not found in the manufacturer datasheet alone.
Alternatives de remplacement direct pour ADS6425IRGC25 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec ADS6425IRGC25 (même facteur de forme et même empreinte) — différant par Package, Number of Channels, Digital Supply Voltage, Input Type, Resolution.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
ADS6425IRGCR
✅ Remplacement direct✓ En stock
$23.1 / unité
Voir la fiche technique →ADS6424IRGC25
✅ Remplacement direct✓ En stock
$31.2 / unité
Voir la fiche technique →ADS6423IRGC25
✅ Remplacement direct✓ En stock
$15.6 / unité
Voir la fiche technique →ADS6422IRGC25
✅ Remplacement direct✓ En stock
$14.95 / unité
Voir la fiche technique →ADS6424IRGCR
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
ADS6423IRGCR
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$21.85 / unité
Voir la fiche technique →ADS6425IRGC25 Valeurs maximales et caractéristiques électriques
| Résolution | 12 bit |
| Number of Channels | 4 |
| Sample Rate (max) | 125 MSPS |
| Architecture | Pipelined |
| Input Type | Single-ended / Differential |
| Output Interface | Serial LVDS (1/2/4-lane modes) |
| Analog Supply Voltage | 3.3 V |
| Digital Supply Voltage | 1.8 V (LVDS) |
| Reference | Internal (with external bypass option) |
| Température de fonctionnement | -40C to +85C (industrial) |
| Boîtier | 64-pin VQFN (RGC) 9 mm x 9 mm |
| Type de montage | Surface Mount |
| Lead-Free / RoHS | Yes / Compliant |
| Exposed Thermal Pad | Yes (must be soldered to PCB ground) |
Configuration des broches de ADS6425IRGC25
| Broche 1 | AINP_A — Channel A positive analog input |
| Broche 2 | AINN_A — Channel A negative analog input |
| Broche 3 | VREF — Voltage reference (internal); bypass with capacitor |
| Broche 4 | AGND — Analog ground |
| Broche 5 | AVDD — Analog 3.3 V supply |
| Broche 6 | AINP_B — Channel B positive analog input |
| Broche 7 | AINN_B — Channel B negative analog input |
| Broche 8 | AVDD — Analog 3.3 V supply |
| Broche 9 | AGND — Analog ground |
| Broche 10 | AINP_C — Channel C positive analog input |
| Broche 11 | AINN_C — Channel C negative analog input |
| Broche 12 | AVDD — Analog 3.3 V supply |
| Broche 13 | AINP_D — Channel D positive analog input |
| Broche 14 | AINN_D — Channel D negative analog input |
| Broche 15 | AGND — Analog ground |
| Broche 16 | AVDD — Analog 3.3 V supply |
| Broche 17 | CM — Common-mode voltage output (for driver biasing) |
| Broche 18 | AGND — Analog ground |
| Broche 19 | RESET — Hardware reset (active low) |
| Broche 20 | PDN — Power-down (active low) |
| Broche 21 | SCLK — Serial configuration clock |
| Broche 22 | SDATA — Serial configuration data input |
| Broche 23 | SEN — Serial enable (active low) |
| Broche 24 | DRVDD — Digital output driver supply 1.8 V (LVDS) |
| Broche 25 | DRGND — Digital output driver ground |
| Broche 26 | CLKP — Differential clock input positive |
| Broche 27 | CLKN — Differential clock input negative |
| Broche 28 | DRGND — Digital output driver ground |
| Broche 29 | NC — Not connected (no internal bond) |
| Broche 30 | NC — Not connected (no internal bond) |
| Broche 31 | DRVDD — Digital output driver supply 1.8 V (LVDS) |
| Broche 32 | DRGND — Digital output driver ground |
| Broche 33 | OUTAP — Channel A LVDS data output positive |
| Broche 34 | OUTAN — Channel A LVDS data output negative |
| Broche 35 | OUTBP — Channel B LVDS data output positive |
| Broche 36 | OUTBN — Channel B LVDS data output negative |
| Broche 37 | DRGND — Digital output driver ground |
| Broche 38 | DRVDD — Digital output driver supply 1.8 V (LVDS) |
| Broche 39 | OUTCP — Channel C LVDS data output positive |
| Broche 40 | OUTCN — Channel C LVDS data output negative |
| Broche 41 | OUTDP — Channel D LVDS data output positive |
| Broche 42 | OUTDN — Channel D LVDS data output negative |
| Broche 43 | FRP — LVDS frame positive output |
| Broche 44 | FRN — LVDS frame negative output |
| Broche 45 | DRGND — Digital output driver ground |
| Broche 46 | DRVDD — Digital output driver supply 1.8 V (LVDS) |
| Broche 47 | CLKOUTP — LVDS bit-clock output positive |
| Broche 48 | CLKOUTN — LVDS bit-clock output negative |
| Broche 49 | DRGND — Digital output driver ground |
| Broche 50 | NC — Not connected |
| Broche 51 | NC — Not connected |
| Broche 52 | NC — Not connected |
| Broche 53 | NC — Not connected |
| Broche 54 | NC — Not connected |
| Broche 55 | NC — Not connected |
| Broche 56 | NC — Not connected |
| Broche 57 | NC — Not connected |
| Broche 58 | NC — Not connected |
| Broche 59 | NC — Not connected |
| Broche 60 | NC — Not connected |
| Broche 61 | NC — Not connected |
| Broche 62 | NC — Not connected |
| Broche 63 | NC — Not connected |
| Broche 64 | NC — Not connected (data pad area) |
Applications typiques
ADS6425IRGC25 convient pour 6 applications: Medical Ultrasound Beamformer Receivers, Multi-Channel Communications Test Equipment, Phased-Array Radar Signal Digitization, Industrial Inspection and Machine Vision, Software-Defined Radio Receiver Front-Ends, Optical Coherence Tomography (OCT) Imaging.
Medical Ultrasound Beamformer Receivers
The ADS6425IRGC25's four simultaneously sampling 12-bit 125 MSPS channels provide correlated multi-channel capture required for phased-array ultrasound beamforming. Place the part downstream of LNA and time-gain-compensation stages; the serial LVDS output collapses the parallel data path onto a small number of differential pairs, reducing board area between the analog front-end and the FPGA beamformer. With four channels per IC, a 32-channel ultrasound probe can be built from only eight ADS6425 devices - half the board space of a parallel-output ADC array and with tightly controlled inter-channel skew because the four channels share the same clock and reference network.
Recommandé
Multi-Channel Communications Test Equipment
For wireless base-station testers and protocol analyzers, the ADS6425IRGC25 provides four 12-bit 125 MSPS channels that capture I/Q streams or multi-antenna signals in a single compact package. Its 3.3 V analog and 1.8 V digital supplies integrate easily with FPGA-based digital down-converters on the same board. The serial LVDS output (1/2/4-lane programmable) lets designers trade throughput per lane against FPGA pin count - use 4-lane mode for maximum throughput, 1-lane mode when FPGA I/O is constrained. The pipelined architecture with integrated input buffers simplifies the analog front-end by eliminating the need for external sample-and-hold circuitry.
Recommandé
Phased-Array Radar Signal Digitization
Phased-array radar sub-arrays require tight inter-channel synchronization and small footprint per channel. The ADS6425IRGC25 delivers four synchronized 125 MSPS converters in one 9 mm x 9 mm VQFN, allowing high channel density while minimizing the analog-to-digital skew that corrupts beam-formed outputs. Designers typically clock the four channels from a common low-jitter source so timing alignment across the sub-array is preserved. The serial LVDS outputs feed directly into FPGA-based digital beamforming logic. At 12-bit, the dynamic range is appropriate for surveillance and weather radar; higher-resolution radars should consider the ADS58C28 family.
Recommandé
Industrial Inspection and Machine Vision
Multi-spectral industrial cameras and X-ray inspection systems require simultaneous sampling of multiple sensor channels to preserve alignment between views. The ADS6425IRGC25's four channels sharing one clock tree provide the deterministic inter-channel latency that vision algorithms require, and the 12-bit resolution is adequate for moderate-dynamic-range imaging. The serial LVDS interface feeds a small FPGA that performs line-scan correlation and defect detection. The 9 mm x 9 mm footprint allows high-density PCB layouts in compact industrial enclosures, and the industrial temperature range (-40C to +85C) suits factory-floor environments.
Recommandé
Software-Defined Radio Receiver Front-Ends
Wideband SDR receivers digitize IF signals at 70-100 MHz with sample rates of 125 MSPS or higher; the ADS6425IRGC25 fits nicely into direct-IF sampling architectures where four channels handle diversity or multi-band reception. The internal reference eliminates external reference noise and drift, and the serial LVDS interface simplifies routing to the FPGA signal-processing fabric. Designers should budget SNR carefully at 70 MHz IF; per TI characterization the ADS6425 is optimized for IF inputs in the 10-70 MHz range while still being usable to 100 MHz with reduced performance.
Recommandé
Optical Coherence Tomography (OCT) Imaging
Spectral-domain OCT requires low-noise, high-linearity analog-to-digital conversion of interferometric signals from a line-scan spectrometer. The ADS6425IRGC25's four synchronized 125 MSPS channels enable simultaneous capture of multiple spectrometer channels or a reference interferometer alongside the sample arm. The 12-bit resolution and pipelined architecture deliver the dynamic range needed for sensitivity beyond -100 dB. The serial LVDS interface minimizes the analog-to-FPGA trace count, reducing crosstalk into the sensitive photodiode front-end. Operating from 3.3 V analog and 1.8 V digital supplies helps the system stay within IEC 60601 medical safety limits for patient-applied isolation budgets.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour ADS6425IRGC25 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | ADS6425IRGCR | ADS6424IRGC25 | ADS6423IRGC25 | ADS6422IRGC25 | ADS6424IRGCR |
|---|---|---|---|---|---|---|
| Package | VQFN-64 (RGC) 9x9 mm | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Max Sample Rate | 125 MSPS | 125 MSPS | 105 MSPS | 80 MSPS | 65 MSPS | 105 MSPS |
| Number of Channels | 4 | 4 | 4 | 4 | 4 | 4 |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Output Interface | Serial LVDS (1/2/4 lanes) | Serial LVDS (1/2/4 lanes) | Serial LVDS (1/2/4 lanes) | Serial LVDS (1/2/4 lanes) | Serial LVDS (1/2/4 lanes) | Serial LVDS (1/2/4 lanes) |
| Analog Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Digital Supply (LVDS) | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Principaux différenciateurs
- Quad 12-bit 125 MSPS with serial LVDS in compact 9x9 mm VQFN-64 (vs ADS6424IRGC25)
- Maximum sample rate within the same VQFN-64 family (vs ADS6423IRGC25 (80 MSPS), ADS6422IRGC25 (65 MSPS))
- Serial LVDS interface reduces board traces vs parallel CMOS ADCs (vs Generic parallel-CMOS 12-bit quad 125 MSPS ADCs (e.g. AD9228 in different package))
- Single 3.3 V analog + 1.8 V digital supply simplifies power-tree design (vs Older quad ADCs requiring dual-polarity supplies or higher-voltage analog rails)
Notes de conception
LVDS output traces must be routed as 100 ohm differential pairs with matched length (skew under 50 ps for the data/clock/frame group on the same channel). Keep LVDS pairs on inner PCB layers with a continuous ground plane beneath to control characteristic impedance; do not route LVDS above or below noisy supply planes. Place LVDS drivers and the FPGA on the same side of the PCB to avoid vias in the differential path. Maintain 3W spacing from other signal traces to minimize crosstalk. The exposed thermal pad of the VQFN-64 must be soldered to a PCB ground pour of at least 1 square inch per square-inch-of-copper rule for thermal dissipation of approximately 1 W at full-speed quad operation.
Power decoupling is critical for high-speed ADC performance. Place a 0.1 uF ceramic capacitor within 2 mm of each AVDD pin and a bulk 10 uF ceramic close to the analog supply input. Use the same approach for the digital 1.8 V DRVDD supply, which feeds the LVDS drivers - inadequate decoupling here directly causes elevated LVDS common-mode noise and reduced SNR. Keep analog and digital ground returns separate until they join directly underneath the VQFN-64 exposed pad. A ferrite bead between the analog and digital 3.3 V rails can further isolate the noise-sensitive input sampling from the digital-output switching transients.
Three pitfalls to avoid: (1) the exposed thermal pad must be soldered to the PCB ground - skipped this and the internal reference becomes unstable and SNR degrades by 5-10 dB; (2) the clock input CLKP/CLKN must be driven by a low-jitter (< 1 ps RMS) differential source - the SNR directly tracks clock jitter, especially at high input frequencies; (3) the LVDS outputs work only with 100 ohm termination - absent termination, the bit-error pattern shows ringing and the FPGA's CDR may fail to lock. Always consult the official datasheet section 'Recommended Operating Conditions' before finalizing the BOM.
Estimated: at 125 MSPS per channel (4 channels active) and 3.3 V AVDD, the part dissipates approximately 600-900 mW total. The 64-pin VQFN with the exposed pad soldered to a 1 square inch copper pour on a 4-layer FR4 board yields a theta-JA of roughly 25 C/W. To keep junction temperature below 125 C in a 70 C ambient, the thermal pad copper should be at least 1 square inch; larger pours (multiple square inches, thermal vias to internal ground planes) are recommended for fanless industrial enclosures. Always place the thermal pad via pattern (0.3 mm holes on 1 mm grid, plated shut or filled with epoxy to prevent solder wicking) directly beneath the device's exposed pad.
Informations de conformité
RoHS compliant per Texas Instruments product page. Industrial-grade (-40C to +85C) only - AEC-Q100 not applicable as this part is not targeted at automotive applications.
