ADS821E - 10-Bit 40MSPS ADC w/ Internal Reference | TI/Burr-Brown
Référence : ADS821E ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $12.45 | $12,45 |
| 10 | $11.2 | $112,00 |
| 100 | $9.85 | $985,00 |
| 500 | $8.5 | $4 250,00 |
| 1 000 | $7.4 | $7 400,00 |
ADS821E Présentation
A successive-approximation-register (SAR) ADC, the ADS821E operates by sampling an input voltage once per conversion cycle and comparing it to an internal binary-weighted capacitor network through a precision comparator; unlike pipelined ADCs, the SAR architecture is fully specified on a single clock edge with no pipeline latency. SAR ADCs occupy a tier below flash ADCs in conversion speed but above delta-sigma ADCs in raw sample rate, and are widely deployed in industrial measurement, data acquisition, and instrumentation. The 28-pin SSOP package places all analog and digital pins on opposite sides of the die to minimize coupling and ease PCB layout separation.
Key features include an internal 2.5 V reference (which can be overdriven externally), a track-and-hold amplifier front-end capable of handling input bandwidths well beyond Nyquist for undersampling applications, low differential nonlinearity for accurate code-edge transitions, and an output enable pin for bus multiplexing. The proprietary architecture provides excellent dynamic performance with spurious-free dynamic range suitable for IF-sampling communications receivers. Power-down mode reduces standby consumption to a few milliwatts for battery-portable designs.
Typical applications include digital oscilloscopes and waveform digitizers, IF sampling for communications receivers, CCD imaging digitizers, portable medical imaging, baseband quadrature sampling in software-defined radios, and general-purpose high-speed data acquisition. The 40 MSPS sample rate and 10-bit resolution are well matched to display refresh rates and pixel-clock-driven video systems.
When designing with this device, decouple the analog supply (AVDD) and digital supply (DVDD) domains separately with 0.1 µF ceramic capacitors placed within 5 mm of the supply pins. Maintain a single-point ground star connection under the AGND/DGND pins to avoid digital switching noise corrupting the analog input. Drive the analog input from a low-impedance, bandwidth-appropriate buffer for best spurious performance.
This page synthesizes distributor pricing, drop-in alternatives from the same ADS82x family and pin-compatible same-package alternatives, and practical PCB layout notes not consolidated in the manufacturer datasheet.
Alternatives de remplacement direct pour ADS821E — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec ADS821E (même facteur de forme et même empreinte) — différant par Package, Architecture, Resolution, Input Type, Data Interface.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
ADS822EG4
✅ Remplacement direct✓ En stock
$4.8 / unité
Voir la fiche technique →ADS823E
✅ Remplacement direct✓ En stock
Contactez-nous pour le prix
Voir la fiche technique →ADS825E
✅ Remplacement direct✓ En stock
Contactez-nous pour le prix
Voir la fiche technique →ADS826E
✅ Remplacement direct✓ En stock
Contactez-nous pour le prix
Voir la fiche technique →AD9226ARSZ
✅ Remplacement direct✓ En stock
$23.4 / unité
Voir la fiche technique →AD9280ARSZ
✅ Remplacement direct✓ En stock
$5.15 / unité
Voir la fiche technique →ADS821E Valeurs maximales et caractéristiques électriques
| Résolution | 10 bits |
| Sample Rate | 40 MSPS (max) |
| Number of Input Channels | 1 |
| Input Type | Single-ended or differential |
| Effective Number of Bits (ENOB) | 9.3 bits |
| Signal-to-Noise Ratio (SNR) | 58 dB |
| Architecture | SAR (Successive Approximation) |
| Analog Supply Voltage (AVDD) | +5 V (typ) |
| Digital Supply Voltage (DVDD) | +5 V (or 3 V logic capable) |
| Power Dissipation | 380 mW (typ) |
| Internal Reference | 2.5 V (internal, externally overdrivable) |
| Plage de température de fonctionnement | -40 C to +85 C (industrial) |
| Boîtier | 28-pin SSOP (DB) |
| Type de montage | Surface Mount |
Configuration des broches de ADS821E
| Broche 1 | OE — Output enable (active low) - tri-states the data bus |
| Broche 2 | DB9 (MSB) — Bit 9 (most significant) of 10-bit parallel output bus |
| Broche 3 | DB8 — Bit 8 of 10-bit parallel output bus |
| Broche 4 | DB7 — Bit 7 of 10-bit parallel output bus |
| Broche 5 | DB6 — Bit 6 of 10-bit parallel output bus |
| Broche 6 | DB5 — Bit 5 of 10-bit parallel output bus |
| Broche 7 | DB4 — Bit 4 of 10-bit parallel output bus |
| Broche 8 | DB3 — Bit 3 of 10-bit parallel output bus |
| Broche 9 | DB2 — Bit 2 of 10-bit parallel output bus |
| Broche 10 | DB1 — Bit 1 of 10-bit parallel output bus |
| Broche 11 | DB0 (LSB) — Bit 0 (least significant) of 10-bit parallel output bus |
| Broche 12 | DGND — Digital ground return for CMOS output drivers |
| Broche 13 | DVDD — Digital supply (+3 V or +5 V, decoupling required) |
| Broche 14 | NC — Not connected (per datasheet) |
| Broche 15 | NC — Not connected (per datasheet) |
| Broche 16 | AVDD — Analog supply (+5 V nominal), decoupling required |
| Broche 17 | AGND — Analog ground - star connection point for analog return |
| Broche 18 | REF — Internal 2.5 V reference output / external reference input |
| Broche 19 | NC — Not connected (per datasheet) |
| Broche 20 | NC — Not connected (per datasheet) |
| Broche 21 | AIN- — Inverting analog input (differential operation) |
| Broche 22 | AIN+ — Non-inverting analog input (single-ended or differential) |
| Broche 23 | AGND — Analog ground tie for input amp |
| Broche 24 | AVDD — Analog supply (mirror pin to pin 16) |
| Broche 25 | PWDN — Power-down (active high) for low-standby mode |
| Broche 26 | CONVST — Conversion start / sample clock input |
| Broche 27 | CS — Chip select for parallel output bus (active low) |
| Broche 28 | BUSY — Conversion-in-progress indicator (open-drain active low) |
Applications typiques
ADS821E convient pour 7 applications: Digital Oscilloscope / Waveform Digitizer, IF Sampling for Communications Receivers, CCD / Image Sensor Digitizer, Battery-Portable Medical Imaging, Baseband Quadrature Sampling (Software-Defined Radio), General-Purpose Data Acquisition (DAQ) Boards, Industrial Automation Test Equipment.
Digital Oscilloscope / Waveform Digitizer
The ADS821E's 40 MSPS sample rate and 10-bit resolution are well matched to mid-bandwidth oscilloscope and waveform digitizer front-ends. With 9.3 effective bits and 58 dB SNR, the converter captures repetitive transients with code-edge resolution suitable for triggering and edge-timing analysis. Placed between the analog front-end attenuator/probe amplifier and the FPGA-based timebase, the ADS821E delivers one conversion per clock cycle with no pipeline delay, which simplifies trigger-event timing. At +5 V supply and 380 mW typical dissipation, a battery-portable scope can power the ADC plus a few op-amps from a small Li-ion regulator; the part's industrial -40 C to +85 C range is acceptable for bench and field instruments.
Recommandé
IF Sampling for Communications Receivers
In an IF-sampling superheterodyne digitizer, the ADS821E samples at 40 MSPS from a 5 MHz to 20 MHz IF strip and delivers 10-bit digital I/Q downconversion in the FPGA. The SAR topology's excellent wideband linearity and 58 dB SNR support demodulation of QAM, QPSK, and OOK carrier structures from baseband to roughly 20 MHz. The internal 2.5 V reference trims part-to-part gain variation and the differential input port accepts a center-tapped IF transformer output, which suppresses even-order harmonics. Because the ADS821E accepts an external clock up to 40 MHz, the same ADC can be reused for low-IF (455 kHz) digital receivers; the wide analog input bandwidth permits undersampling of pulsed RF up to ~70 MHz.
Recommandé
CCD / Image Sensor Digitizer
Industrial and scientific line-scan or area CCD arrays commonly produce pixel rates at or below 40 MPixel/s, well within the ADS821E's 40 MSPS sample ceiling. The 10-bit gray-scale resolution provides 1024 intensity levels, sufficient for machine-vision edge detection, OCR, and bar-code scanners where 12-bit+ dynamic range is unnecessary. The internal sample-and-hold absorbs the CCD clock-feedthrough transient, presenting a clean settled voltage to the SAR comparator each pixel period. Driving the analog input with a low-impedance emitter follower preserves the SFDR; pin-compatibility with the ADS826E (60 MSPS) allows the same PCB to support higher line-rate camera heads by simple ODM swap.
Recommandé
Battery-Portable Medical Imaging
Diagnostic ultrasound front-ends and portable pulse-oximeter ASICs often specify 10-bit/40 MSPS ADC channels for low-power color-flow imaging and Doppler demodulation. The ADS821E draws only 380 mW from +5 V, allowing a small handheld device to power several channels from a Li-ion source through a 3.3 V to 5 V boost converter. Its 58 dB SNR preserves sufficient dynamic range for envelope detection of weak return signals, and the differential input structure rejects common-mode noise from the switching boost regulator. The 28-pin SSOP lands inside the small footprint of a 40 mm-by-60 mm handheld probe housing, leaving room for the transducer interface and isolation barrier.
Recommandé
Baseband Quadrature Sampling (Software-Defined Radio)
In an SDR baseband chain, two ADS821E channels can simultaneously sample the I and Q demodulated baseband outputs of an I/Q mixer at up to 40 MSPS, providing 20 MHz of usable I/Q bandwidth. The 10-bit resolution directly captures all but the weakest digital-modulation constellations (256-QAM needs ~10 bits at 30 dB SNR), making the ADC ideal for narrowband ham/HF SDR experiments and commercial sub-20 MHz receivers. SAR latency of one clock allows frame-triggered burst sampling. The pin-compatible ADS826E gives 60 MSPS for wider-bandwidth SDR variants on the same PCB platform, avoiding a respin of the analog front-end.
Recommandé
General-Purpose Data Acquisition (DAQ) Boards
PCI/PCMCIA and USB DAQ cards frequently need a 40 MSPS/10-bit acquisition path for transient capture, sonar arrays, vibration monitoring, and bench instrumentation. The ADS821E fits between an input protection network (resistor divider and clamp diode) and an FPGA/CPLD DMA engine that bursts samples into on-board memory. SAR's single-clock latency makes it easy to timestamp records precisely against an external trigger, while the parallel CMOS output bus minimizes interface complexity in DSP glue logic. By dropping in the pin-compatible ADS825E (with input buffer), the same BOM can support low-impedance transducer sources without a re-layout.
Recommandé
Industrial Automation Test Equipment
Automated test racks for sensor calibration and motor control feedback loops typically need moderate-speed, moderate-resolution ADCs for sensing current, vibration, and position signals. The ADS821E's 9.3 ENOB and 40 MSPS rate sample complex PWM-driven waveforms and capture switching-transistor ringing within one switching cycle (typically 10 to 25 microseconds at 40 kHz). The SSOP-28 industrial-grade (-40 C to +85 C) package tolerates the thermal environment of a sealed control cabinet. Single +5 V operation integrates with the 5 V rails already common in PLC backplanes; pin compatibility with the buffered ADS825E allows lower-impedance transducer drivers without changing the PCB.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour ADS821E — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | ADS822E | ADS823E | ADS825E | ADS826E | AD9226ARSZ |
|---|---|---|---|---|---|---|
| Package | 28-SSOP (DB) | 28-SSOP (DB) - same | 28-SSOP (DB) - same | 28-SSOP (DB) - same | 28-SSOP (DB) - same | 28-SSOP - same footprint family |
| Brand | Texas Instruments (Burr-Brown) | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Analog Devices |
| Resolution | 10 bits | 10 bits | 10 bits | 10 bits | 10 bits | 12 bits |
| Sample Rate | 40 MSPS | 40 MSPS | 60 MSPS | 40 MSPS | 60 MSPS | 65 MSPS |
| Input Buffer On-Chip | No (raw SAR input) | Yes (buffered) | No (raw) | Yes (buffered) | Yes (buffered) | Yes (buffered) |
| Power Dissipation (typ) | 380 mW | 380 mW | 475 mW | 380 mW | 475 mW | 475 mW |
| SNR (typ) | 58 dB | 58 dB | 57 dB | 58 dB | 57 dB | 69 dB |
| Supply Voltage | +5 V (single) | +5 V (single) | +5 V (single) | +5 V (single) | +5 V (single) | +5 V (single) |
| Lifecycle Status | N/R (Not Recommended for new design) | N/R | N/R | N/R | N/R | Active |
Principaux différenciateurs
- Unbuffered input for lowest total noise (vs ADS822E)
- Lower sample rate, lower power for cost-optimized designs (vs ADS823E)
- Raw SAR input for full-accuracy sampling (vs ADS825E)
- Long-term Rochester Electronics inventory only (vs AD9226ARSZ (Analog Devices))
Notes de conception
The ADS821E requires separate decoupling on AVDD (pin 16, 24) and DVDD (pin 13). Place 0.1 uF X7R ceramic capacitors within 5 mm of each supply pin, in parallel with a 10 uF tantalum or ceramic bulk capacitor to handle transient switching currents of the digital output bus. Estimated: at 40 MSPS with 10 pF load on each output driver, transient supply current can exceed 100 mA peak, which mandates a low-impedance bypass network. Sharing AVDD and DVDD bypassing or omitting one will inject switching transients into the comparator and degrade SNR.
Maintain a star-ground topology under the AGND (pin 17, 23) and DGND (pin 12) pins: route analog and digital grounds from independent planes to a single point below the IC, preventing digital return currents from flowing through the analog ground. Keep the analog input traces (AIN+/AIN-) short and guard them with a ground-fill on both sides of the SSOP. The CLK/CONVST traces should also be short to minimize digital coupling into the analog input. Refer to TI's layout checklist for SAR ADC reference designs when designing the SSOP-28 PCB footprint.
The SAR input draws a transient kickback current at the start of each conversion because the internal binary-weighted capacitor array must be disconnected from the input and then reconnected with the input voltage sampled on its array. Driving this kickback requires a low-impedance source - typically a wideband op-amp like the AD8055 or a transformer with low secondary impedance. Inadequate drive impedance increases distortion (THD) and reduces effective bits (ENOB). A resistor of 5 to 50 ohm in series between the op-amp output and AIN+ can sometimes dampen the kickback, but most designs simply require a faster driver amplifier.
The SSOP-28 package dissipates 380 mW typical (470 mW worst-case at 40 MSPS). The 28-SSOP has a theta_JA of approximately 80 C/W on a 4-layer PCB (JEDEC JESD51-7 standard), which yields a junction temperature rise of ~30 C above ambient at typical power. Keep ambient below +55 C to maintain junction under +85 C, allowing margin for warm enclosures. No external heatsink is required because the absolute maximum junction temperature is +150 C. Estimated: theta_JA = 80 C/W is a typical SSOP-28 figure; datasheet should be checked against actual test conditions.
Do not operate AVDD without DVDD or vice versa - the ADS821E's ESD structures may be stressed. Always tie the NC (no-connect) pins on the SSOP-28 footprint (pins 14, 15, 19, 20) to a non-functional trace or leave them floating; do not connect them to supplies or ground. Ensure the external oscillator driving CONVST has CMOS-level swing and < 1 ns jitter - jitter directly degrades SNR at full-scale input. Finally, do not rely on the internal 2.5 V reference for absolute accuracy of better than +/- 0.5% without load regulation check - bypass REF (pin 18) with a 2.2 uF low-leakage capacitor if precision matters.
Informations de conformité
RoHS / REACH / lead-free / halogen-free status not stated in the provided web snippets; lifecycle is 'Not Recommended for new design' per TI's web portal. AEC-Q100 not applicable (industrial-grade ADC for instrumentation). Conflict-mineral compliance per TI standard practice.
