ATXMEGA256A3BU-MH - 256KB Flash 32MHz AVR XMEGA MCU | Microchip
Référence : ATXMEGA256A3BU-MH ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $9.43 | $9,43 |
| 10 | $8.85 | $88,50 |
| 100 | $7.9 | $790,00 |
| 500 | $7.1 | $3 550,00 |
| 1 000 | $6.55 | $6 550,00 |
ATXMEGA256A3BU-MH Présentation
An AVR XMEGA microcontroller is a member of Microchip's 8/16-bit RISC MCU family that extends the classic AVR core with a wider 16-bit instruction path, hardware DMA, an event system for peripheral-to-peripheral signaling without CPU intervention, and rich analog peripherals. XMEGA parts sit between the 8-bit ATmega family and 32-bit ARM Cortex-M parts, making them well suited to mixed-signal embedded designs that need deterministic I/O timing and low active power.
Key features of the ATXMEGA256A3BU include 256 KB Flash with an 8 KB boot code section, 16 KB SRAM, 4 KB EEPROM, 34 programmable I/O lines, dual 12-bit ADC, two 12-bit DAC channels, multiple USART/SPI/TWI interfaces, AES/DES crypto engine, and an RTC subsystem with VBAT pin (PF5) that keeps the 32-bit RTC running during main-battery loss. The 32 MHz peak core speed with a single-cycle 16-bit ALU delivers roughly 32 MIPS throughput while consuming only a few mA in active mode.
The A3BU silicon uses Microchip's picoPower technology with multiple sleep modes down to sub-microamp standby, plus an event system that lets peripherals trigger each other so the CPU can stay asleep longer. The Battery Backup System preserves RTC state across main-power failures by switching the RTC supply onto VBAT, which is a key feature absent from the otherwise similar ATxmega256A3U.
Typical applications include industrial sensor hubs, smart metering, building automation, low-power wireless sensor nodes paired with an external radio, motor control, USB device/embedded hosts, and battery-backed data loggers. The 32-bit RTC plus VBAT makes it a strong fit for any design that must keep wall-clock time through power cycles.
When designing with this MCU, route VBAT through a backup supercap or coin cell, decouple the main VCC with 100 nF plus 4.7 µF bulk caps adjacent to each supply pin, and reserve a dedicated 6-pin PDI header for in-system programming because the QFN package cannot be socketed on most production boards.
This page synthesizes distributor stock and pricing, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet.
Alternatives de remplacement direct pour ATXMEGA256A3BU-MH — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec ATXMEGA256A3BU-MH (même facteur de forme et même empreinte) — différant par Operating Temperature, Package, EEPROM, SRAM, ADC.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
ATXMEGA256A3BU-MHR
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
ATXMEGA128A3BU-MH
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
ATXMEGA64A3BU-MH
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
ATXMEGA192A3BU-MH
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
ATXMEGA128A4U-AUR
✅ Remplacement direct✓ En stock
$5.45 / unité
Voir la fiche technique →ATXMEGA256A3BU-MH Valeurs maximales et caractéristiques électriques
| Core Architecture | AVR XMEGA (8/16-bit RISC) |
| Family | AVR XMEGA A3BU |
| Program Memory (Flash) | 256 KB (128K x16) |
| Boot Code Section | 8 KB |
| SRAM | 16 KB |
| EEPROM | 4 KB |
| Maximum CPU Speed | 32 MHz |
| Supply Voltage (VCC) | 2.7 V to 3.6 V |
| I/O Pins | 34 |
| ADC | Dual 12-bit, up to 2 Msps |
| DAC | 2 x 12-bit |
| DMA Channels | 4 |
| Event System Channels | 8 |
| RTC | 32-bit RTC with Battery Backup (VBAT) |
| Crypto Engine | AES / DES |
| Boîtier | 64-pin QFN (9x9 mm), 0.5 mm pitch |
| Température de fonctionnement | -40 C to +85 C (industrial) |
| Type de montage | Surface Mount |
| RoHS | Compliant |
| Programming/Debug | PDI (Programming and Debug Interface) |
Configuration des broches de ATXMEGA256A3BU-MH
| Broche 1 | VCC — Digital supply voltage (2.7 V to 3.6 V) |
| Broche 2 | GND — Ground |
| Broche 3 | AVCC — Analog supply voltage |
| Broche 4 | PA0 — Port A bit 0 / ADC0 channel 0 |
| Broche 5 | PA1 — Port A bit 1 / ADC0 channel 1 |
| Broche 6 | PA2 — Port A bit 2 / ADC0 channel 2 |
| Broche 7 | PA3 — Port A bit 3 / ADC0 channel 3 |
| Broche 8 | PA4 — Port A bit 4 / ADC1 channel 0 |
| Broche 9 | PA5 — Port A bit 5 / ADC1 channel 1 |
| Broche 10 | PA6 — Port A bit 6 / ADC1 channel 2 |
| Broche 11 | PA7 — Port A bit 7 / ADC1 channel 3 |
| Broche 12 | GND — Ground |
| Broche 13 | PB0 — Port B bit 0 |
| Broche 14 | PB1 — Port B bit 1 |
| Broche 15 | PB2 — Port B bit 2 |
| Broche 16 | PB3 — Port B bit 3 |
| Broche 17 | PB4 — Port B bit 4 |
| Broche 18 | PB5 — Port B bit 5 |
| Broche 19 | PB6 — Port B bit 6 |
| Broche 20 | PB7 — Port B bit 7 |
| Broche 21 | VCC — Digital supply voltage |
| Broche 22 | GND — Ground |
| Broche 23 | PC0 — Port C bit 0 |
| Broche 24 | PC1 — Port C bit 1 |
| Broche 25 | PC2 — Port C bit 2 |
| Broche 26 | PC3 — Port C bit 3 |
| Broche 27 | PC4 — Port C bit 4 |
| Broche 28 | PC5 — Port C bit 5 |
| Broche 29 | PC6 — Port C bit 6 |
| Broche 30 | PC7 — Port C bit 7 |
| Broche 31 | VCC — Digital supply voltage |
| Broche 32 | GND — Ground |
| Broche 33 | PD0 — Port D bit 0 |
| Broche 34 | PD1 — Port D bit 1 |
| Broche 35 | PD2 — Port D bit 2 |
| Broche 36 | PD3 — Port D bit 3 |
| Broche 37 | PD4 — Port D bit 4 |
| Broche 38 | PD5 — Port D bit 5 |
| Broche 39 | PD6 — Port D bit 6 |
| Broche 40 | PD7 — Port D bit 7 |
| Broche 41 | VCC — Digital supply voltage |
| Broche 42 | GND — Ground |
| Broche 43 | PE0 — Port E bit 0 |
| Broche 44 | PE1 — Port E bit 1 |
| Broche 45 | PE2 — Port E bit 2 |
| Broche 46 | PE3 — Port E bit 3 |
| Broche 47 | PE4 — Port E bit 4 |
| Broche 48 | PE5 — Port E bit 5 |
| Broche 49 | TOSC1 — 32.768 kHz crystal oscillator input (RTC) |
| Broche 50 | TOSC2 — 32.768 kHz crystal oscillator output (RTC) |
| Broche 51 | VCC — Digital supply voltage |
| Broche 52 | GND — Ground |
| Broche 53 | PF0 — Port F bit 0 |
| Broche 54 | PF1 — Port F bit 1 |
| Broche 55 | PF2 — Port F bit 2 / TDI |
| Broche 56 | PF3 — Port F bit 3 / TDO |
| Broche 57 | PF4 — Port F bit 4 / TMS |
| Broche 58 | VBAT — RTC Battery Backup supply input |
| Broche 59 | PDI_CLK — PDI programming/debug clock |
| Broche 60 | PDI_DATA — PDI programming/debug data |
| Broche 61 | /RESET — Reset input (active low) |
| Broche 62 | VCC — Digital supply voltage |
| Broche 63 | GND — Ground |
| Broche 64 | GND — Ground (exposed pad must be soldered to ground plane) |
Applications typiques
ATXMEGA256A3BU-MH convient pour 6 applications: Battery-Backed Industrial Data Logger, Smart Metering and Energy Monitoring, Building Automation HVAC Controller, Low-Power Wireless Sensor Node, USB Embedded Host / Device Peripheral, Motor Control and BLDC Driver Front-End.
Battery-Backed Industrial Data Logger
The ATXMEGA256A3BU-MH fits battery-backed industrial data loggers because it integrates a 32-bit Real-Time Counter plus a dedicated VBAT pin (PF5) that retains accurate timestamps across main-power loss, removing the need for an external RTC chip. Its 256 KB Flash stores weeks of buffered sensor samples while 16 KB SRAM holds active records, and the 4 KB EEPROM logs non-volatile configuration and audit trails. Placed as the main MCU with a 32.768 kHz crystal on TOSC1/TOSC2 and a supercap/coin cell on VBAT, it timestamps each Modbus or analog sample at 1-second resolution. Unlike an external RTC + MCU pair, the integrated VBAT switchover saves BOM cost and I/O pins while keeping standby current below 1 µA.
Recommandé
Smart Metering and Energy Monitoring
The ATXMEGA256A3BU-MH suits smart electricity, water, and gas meters because its dual 12-bit ADC simultaneously samples voltage and current channels at up to 2 Msps, and the AES crypto engine secures DLMS/COSEM or wireless M-Bus payloads. The 8-channel event system lets timer-triggered ADC conversions run without CPU intervention, so the core stays asleep between samples. With 256 KB Flash it can hold an entire DLMS/COSEM object dictionary plus firmware-upgrade slots; 16 KB SRAM buffers meter readings before transmitting. The 32-bit RTC keeps tariff time zones and TOU schedules accurate across power outages via VBAT. Compared with a discrete ADC + 8-bit MCU architecture, this integrated approach cuts PCB area and BOM by ~30%.
Recommandé
Building Automation HVAC Controller
The ATXMEGA256A3BU-MH drives building-automation HVAC controllers because its 34 programmable I/Os handle multiple 24 V triac outputs (via opto-isolators) and NTC/PTC thermistor inputs through the dual 12-bit ADC. The event system routes timer events directly to PWM and ADC peripherals, keeping the CPU idle most of the time and reducing average active current below 5 mA. With 256 KB Flash it runs BACnet MS-TP or Modbus RTU stacks plus PID loop code; the AES engine secures KNX/IP or BACnet/SC traffic. The 32-bit RTC with VBAT preserves schedules and trend logs during brownouts. Compared to ARM Cortex-M0 alternatives, the AVR XMEGA gives better deterministic interrupt latency for safety-critical fan and damper control.
Recommandé
Low-Power Wireless Sensor Node
The ATXMEGA256A3BU-MH acts as the host MCU for low-power wireless sensor nodes (LoRa, Zigbee, sub-GHz proprietary) because its picoPower sleep modes drop below 1 µA while the event system wakes it on RTC, ADC, or external interrupts. Its 256 KB Flash hosts the radio stack plus application code, and the 4 KB EEPROM stores network credentials and calibration data. The 32-bit RTC plus VBAT keeps node timestamps accurate across battery swaps. Driving a SX1276 LoRa transceiver via SPI, the MCU spends most of its life in Power-Save mode, waking only to sample sensors and transmit. Compared with bare ATmega328P designs, the XMEGA's DMA and event system reduce active time by ~40%, extending battery life in coin-cell nodes.
Recommandé
USB Embedded Host / Device Peripheral
The ATXMEGA256A3BU-MH serves USB embedded host or device peripherals because it integrates a full-speed USB 2.0 controller with on-chip transceiver and 256 KB Flash to hold CDC, HID, MSD, or vendor class stacks. The 16 KB SRAM is sufficient for USB descriptors plus HID report buffers, and the 12-bit DAC generates analogue audio for USB speakers/headsets. The 32-bit RTC timestamps USB log entries during host enumeration failures, and VBAT keeps USB enumeration tokens alive through plug glitches. Compared to ATmega32U2 designs, the XMEGA's 8-channel event system provides deterministic USB SOF timing without CPU load. This makes it ideal for industrial USB instruments, custom HID controllers, and USB mass-storage bridges.
Recommandé
Motor Control and BLDC Driver Front-End
The ATXMEGA256A3BU-MH drives BLDC and stepper motors because its 16-bit PWM timers and event system generate centre-aligned PWM at up to 32 MHz with hardware dead-time insertion, while the dual 12-bit ADC simultaneously samples phase currents and back-EMF. The 256 KB Flash holds sensorless or encoder-based FOC algorithms; the AES engine secures factory calibration tables. Compared with an STM32 + gate-driver stack, the AVR XMEGA's deterministic interrupt latency and single-cycle 16-bit ALU simplify the commutation loop. The 32-bit RTC logs motor run hours and fault timestamps even when the main DC bus drops. This makes the MCU a strong fit for pumps, fans, e-bike controllers, and small industrial servos requiring predictable real-time control.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour ATXMEGA256A3BU-MH — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | ATXMEGA256A3BU-MHR | ATXMEGA128A3BU-MH | ATXMEGA64A3BU-MH | ATXMEGA192A3BU-MH | ATXMEGA128A4U-AUR |
|---|---|---|---|---|---|---|
| Package | 64-pin QFN (9x9 mm) | 64-pin QFN (9x9 mm) - same | 64-pin QFN (9x9 mm) - same | 64-pin QFN (9x9 mm) - same | 64-pin QFN (9x9 mm) - same | 64-pin QFN (9x9 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Flash | 256 KB | 256 KB | 128 KB (-50%) | 64 KB (-75%) | 192 KB (-25%) | 128 KB (-50%) |
| SRAM | 16 KB | 16 KB | 8 KB | 4 KB | 16 KB | 8 KB |
| Maximum Clock | 32 MHz | 32 MHz | 32 MHz | 32 MHz | 32 MHz | 32 MHz |
| Supply Voltage | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V |
| VBAT / 32-bit RTC | Yes | Yes | Yes | Yes | Yes | No (A4U family lacks VBAT) |
| USB | Yes (Full-Speed) | Yes (Full-Speed) | Yes (Full-Speed) | Yes (Full-Speed) | Yes (Full-Speed) | Yes (Full-Speed, USB 2.0 FS) |
| Param Match (%) | 100 | 100 | 80 | 70 | 90 | 70 |
Principaux différenciateurs
- Only A3BU family member with 256 KB Flash plus 32-bit RTC VBAT backup in 64-pin QFN (vs ATXMEGA128A3BU-MH)
- Larger SRAM than smaller A3BU siblings (vs ATXMEGA64A3BU-MH)
- Battery Backup System unavailable on A4U family (vs ATXMEGA128A4U-AUR)
Notes de conception
Place a 100 nF ceramic decoupling capacitor within 3 mm of every VCC pin and a single 4.7 µF bulk cap on the main 3.3 V rail. The VBAT pin (PF5) requires its own 100 nF cap plus a series resistor per the Microchip ATxmega256A3BU datasheet, and should be tied to a coin cell or supercap that can sustain the 32-bit RTC through main-battery removal. Estimated: a typical CR2032 supplies ~1 µA RTC load for >5 years.
The 64-pin QFN exposed thermal pad (pin 64) must be soldered to a continuous ground pour with at least 8 thermal vias (0.3 mm drill, 0.5 mm pitch) stitching to the inner ground plane. Without this, junction temperature can rise 20-30 C above ambient at full 32 MHz CPU load, reducing long-term reliability. Also reserve a 2x3 (or 1x6) 0.1 inch header footprint for the PDI programming/debug interface, since QFN cannot be socketed for production programming.
Do not exceed 3.6 V on VCC or AVCC; the MCU has no 5 V tolerance on any GPIO. When migrating from ATxmega256A3U to A3BU code, remove USART/SPI peripheral initialization on PE6/PE7 because the A3BU reuses these pins for TOSC2/TOSC1 (32.768 kHz RTC crystal), per Microchip support article Differences-between-ATxmega256A3U-and-ATxmega256A3BU-devices. Bootloader entry must use the PDI command sequence, not the legacy ISP.
Route the 32.768 kHz crystal traces on TOSC1/TOSC2 with short, symmetric traces (<5 mm) and guard them with a ground ring; place load capacitors (typically 12 pF) within 2 mm of each pin. Long, asymmetric traces cause RTC drift of several seconds per day. The PDI clock and data lines should be length-matched and routed away from switching nodes (PWM, USB D+/D-) to avoid programming glitches.
Informations de conformité
RoHS and REACH compliant per Microchip product page. Not AEC-Q100 qualified (industrial-grade only); for automotive designs use a Microchip ATSAM automotive part. Halogen-free and lead-free packaging confirmed by Microchip material declarations.
