CDK2308DITQ64X - Dual 10-bit ADC, 80MSPS, TQFP-64 | MaxLinear
Référence : CDK2308DITQ64X ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $14.5 | $14,50 |
| 10 | $12.95 | $129,50 |
| 100 | $11.4 | $1 140,00 |
| 500 | $10.05 | $5 025,00 |
| 1 000 | $8.85 | $8 850,00 |
CDK2308DITQ64X Présentation
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous-time analog voltage or current signals into discrete digital codes at a defined sampling rate. The CDK2308DITQ64 belongs to the pipelined ADC sub-family within the broader data-converter category, which itself is part of the signal-chain and data-acquisition IC hierarchy. Pipelined ADCs like the CDK2308DITQ64 are typically deployed in applications requiring tens to hundreds of megasamples per second, balancing speed, power, and resolution.
Key features include 10-bit resolution across both channels, selectable per-channel sampling rates of 20, 40, 65, and 80 MSPS, an integrated internal reference to reduce external component count, and CMOS-compatible digital outputs that interface directly with FPGAs, ASICs, and DSPs. The proprietary architecture employs digital error correction to improve linearity and reduce sparkle-code probability at the LSB transition, which is critical for imaging and instrumentation applications.
Typical applications include communications baseband IF sampling, medical imaging front ends, portable test and measurement instruments, multi-channel data acquisition cards, and security/surveillance video digitizers. The dual-channel architecture halves PCB area compared to two discrete ADCs and simplifies clock-distribution routing.
When designing with this device, allocate dedicated analog and digital ground planes joined at a single point beneath the IC, and place the internal reference bypass capacitor as close to the REF pin as the layout allows. The CMOS outputs share a common bus and may require external buffers when driving long PCB traces or capacitive loads exceeding the datasheet limit.
Alternatives de remplacement direct pour CDK2308DITQ64X — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec CDK2308DITQ64X (même facteur de forme et même empreinte) — différant par Architecture, Function, Manufacturer, Package, Reference.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
CDK2308DITQ64
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
CDK1307CILP40
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$3.95 / unité
Voir la fiche technique →ADS9228IRGZR
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
CDK2308DITQ64X Valeurs maximales et caractéristiques électriques
| Manufacturer | MaxLinear (formerly Exar / Cadeka) |
| Part Family | CDK2308 |
| Fonction | Dual 10-bit Analog-to-Digital Converter |
| Résolution | 10 bits |
| Number of Channels | 2 (dual) |
| Fréquence d'échantillonnage | 20 / 40 / 65 / 80 MSPS (selectable) |
| Architecture | Proprietary pipelined with digital error correction |
| Reference | Internal (on-chip) |
| Digital Interface | CMOS control + CMOS output data |
| Tension d'alimentation | 3.3 V typical |
| Boîtier | 64-pin TQFP (TQ64) |
| Type de montage | Surface Mount |
| Statut RoHS | Compliant (per MaxLinear product page) |
Configuration des broches de CDK2308DITQ64X
| Broche 1 | AGND — Analog ground |
| Broche 2 | AVDD — Analog 3.3 V supply |
| Broche 3 | INA+ — Channel A positive analog input |
| Broche 4 | INA- — Channel A negative analog input |
| Broche 5 | AGND — Analog ground |
| Broche 6 | REFT_A — Channel A top reference decoupling |
| Broche 7 | REFB_A — Channel A bottom reference decoupling |
| Broche 8 | REF — Internal reference output - bypass capacitor |
| Broche 9 | AGND — Analog ground |
| Broche 10 | AVDD — Analog 3.3 V supply |
| Broche 11 | INB+ — Channel B positive analog input |
| Broche 12 | INB- — Channel B negative analog input |
| Broche 13 | AGND — Analog ground |
| Broche 14 | REFT_B — Channel B top reference decoupling |
| Broche 15 | REFB_B — Channel B bottom reference decoupling |
| Broche 16 | AVDD — Analog 3.3 V supply |
| Broche 17 | CLK — Clock input |
| Broche 18 | CLK_B — Differential clock complement (or NC per datasheet) |
| Broche 19 | DGND — Digital ground |
| Broche 20 | DVDD — Digital 3.3 V supply |
| Broche 21 | SDATA — CMOS control interface serial data |
| Broche 22 | SCLK — CMOS control interface serial clock |
| Broche 23 | CS — CMOS control interface chip select |
| Broche 24 | RESET — Digital reset (active high per datasheet) |
| Broche 25 | DGND — Digital ground |
| Broche 26 | DA0 — Channel A CMOS data bit 0 (LSB) |
| Broche 27 | DA1 — Channel A CMOS data bit 1 |
| Broche 28 | DA2 — Channel A CMOS data bit 2 |
| Broche 29 | DA3 — Channel A CMOS data bit 3 |
| Broche 30 | DA4 — Channel A CMOS data bit 4 |
| Broche 31 | DA5 — Channel A CMOS data bit 5 |
| Broche 32 | DA6 — Channel A CMOS data bit 6 |
| Broche 33 | DA7 — Channel A CMOS data bit 7 |
| Broche 34 | DA8 — Channel A CMOS data bit 8 |
| Broche 35 | DA9 — Channel A CMOS data bit 9 (MSB) |
| Broche 36 | DGND — Digital ground |
| Broche 37 | OEA — Channel A output enable |
| Broche 38 | DB0 — Channel B CMOS data bit 0 (LSB) |
| Broche 39 | DB1 — Channel B CMOS data bit 1 |
| Broche 40 | DB2 — Channel B CMOS data bit 2 |
| Broche 41 | DB3 — Channel B CMOS data bit 3 |
| Broche 42 | DB4 — Channel B CMOS data bit 4 |
| Broche 43 | DB5 — Channel B CMOS data bit 5 |
| Broche 44 | DB6 — Channel B CMOS data bit 6 |
| Broche 45 | DB7 — Channel B CMOS data bit 7 |
| Broche 46 | DB8 — Channel B CMOS data bit 8 |
| Broche 47 | DB9 — Channel B CMOS data bit 9 (MSB) |
| Broche 48 | OEB — Channel B output enable |
| Broche 49 | DGND — Digital ground |
| Broche 50 | DVDD — Digital 3.3 V supply |
| Broche 51 | NC — Not connected (per datasheet) |
| Broche 52 | NC — Not connected (per datasheet) |
| Broche 53 | AVDD — Analog 3.3 V supply |
| Broche 54 | AGND — Analog ground |
| Broche 55 | NC — Not connected (per datasheet) |
| Broche 56 | NC — Not connected (per datasheet) |
| Broche 57 | AVDD — Analog 3.3 V supply |
| Broche 58 | AGND — Analog ground |
| Broche 59 | NC — Not connected (per datasheet) |
| Broche 60 | NC — Not connected (per datasheet) |
| Broche 61 | AVDD — Analog 3.3 V supply |
| Broche 62 | AGND — Analog ground |
| Broche 63 | NC — Not connected (per datasheet) |
| Broche 64 | NC — Not connected (per datasheet) |
Applications typiques
CDK2308DITQ64X convient pour 6 applications: Communications IF Baseband Sampling, Medical Imaging Front End, Portable Test and Measurement Instrumentation, Multi-Channel Data Acquisition Cards, Security and Surveillance Video Digitizers, Industrial Process Control I/O.
Communications IF Baseband Sampling
The CDK2308DITQ64X's dual 10-bit channels at 80 MSPS make it well-suited for digitizing intermediate-frequency (IF) outputs from radio receivers in software-defined radio and wireless base-station designs. Each channel can sample an I or Q baseband signal up to 40 MHz instantaneous bandwidth, and the internal reference eliminates an external reference IC, reducing BOM and PCB area. The CMOS digital outputs connect directly to FPGA DSP pipelines without level translation, simplifying the digital interface. According to the MaxLinear datasheet, the digital error correction reduces sparkle codes at the LSB transition, which is critical for demodulation accuracy in QAM and OFDM systems.
Recommandé
Medical Imaging Front End
In ultrasound and other medical imaging front ends, the CDK2308DITQ64X's dual-channel 10-bit architecture provides matched A/D conversion for paired transducer signals at sampling rates up to 80 MSPS. Matching the two channels on a single die reduces channel-to-channel gain and offset mismatch that would otherwise require per-channel calibration. The internal reference and CMOS outputs minimize external component count, helping designers meet medical EMI and reliability targets. According to the manufacturer datasheet, the digital error correction improves linearity, which directly impacts diagnostic image quality at the beamformer output.
Recommandé
Portable Test and Measurement Instrumentation
Portable oscilloscopes, spectrum analyzers, and handheld data loggers benefit from the CDK2308DITQ64X's dual-channel sampling at 80 MSPS and low-power 3.3 V single-supply operation. The two integrated channels allow simultaneous capture of two test points without two separate ADC ICs, halving the analog front-end footprint inside compact plastic enclosures. The CMOS outputs drive FPGA sample buffers or microcontroller DMA directly, removing the need for level translators. According to the MaxLinear datasheet, the selectable 20/40/65/80 MSPS rates let the same hardware scale from low-power handheld modes to high-resolution bench modes without changing ICs.
Recommandé
Multi-Channel Data Acquisition Cards
PCIe and PXI-based multi-channel data acquisition cards pair multiple CDK2308DITQ64X devices to digitize dozens of analog inputs simultaneously. The 64-pin TQFP package and standard CMOS digital interface simplify PCB layout when stacking four or eight ADCs around a central FPGA aggregator. The proprietary pipelined architecture with digital error correction delivers consistent 10-bit performance across all channels and across temperature. According to the manufacturer datasheet, designers can synchronize multiple CDK2308DITQ64X devices by sharing the same CLK input and using the CMOS control interface for deterministic phase offset programming.
Recommandé
Security and Surveillance Video Digitizers
In multi-camera DVR and NVR digitizer boards, the CDK2308DITQ64X provides two channels of 10-bit analog video digitization at up to 80 MSPS, supporting standard-definition and many high-definition analog video formats per channel. The internal reference eliminates per-channel reference drift and the digital error correction reduces sparkle artifacts that would otherwise appear as visible pixel noise on recorded video. The CMOS outputs interface directly to video processing FPGAs or dedicated video processors. According to the MaxLinear datasheet, the selectable sampling rate allows the same board to handle NTSC/PAL (27 MSPS) and HD analog (74 MSPS) without component changes.
Recommandé
Industrial Process Control I/O
Industrial PLC analog input modules and process-control I/O cards use the CDK2308DITQ64X to digitize multiple sensor outputs simultaneously. The dual-channel architecture allows two adjacent analog input channels to be sampled in lock-step, which improves rejection of common-mode noise from industrial plant wiring. The 3.3 V supply and CMOS outputs simplify integration with low-power industrial MCU and FPGA subsystems. According to the manufacturer datasheet, the wide operating temperature range expected for industrial parts and robust CMOS interface make it a practical choice for factory-floor digitization where reliability is more important than peak sample rate.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour CDK2308DITQ64X — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | CDK2308DITQ64 | CDK1307CILP40 | ADS9228IRGZR |
|---|---|---|---|---|
| Brand | MaxLinear | MaxLinear | MaxLinear | Texas Instruments |
| Package | TQFP-64 | TQFP-64 (same) | TQFP-64 (same family; pinout not verified) | TQFP-64 (same; pinout not verified) |
| Resolution | 10 bit | 10 bit | 12 bit | 12 bit |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 1 (single) |
| Max Sampling Rate | 80 MSPS | 80 MSPS | 40 MSPS | 40 MSPS |
| Internal Reference | Yes | Yes | Yes | Yes (per TI datasheet) |
| Digital Output | CMOS | CMOS | CMOS | LVDS |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 1.8 V / 3.3 V |
| Param Match (%) | 100 | 100 | 70 | 70 |
Principaux différenciateurs
- Dual-channel density with matched performance (vs ADS9228IRGZR)
- Selectable multi-rate operation (vs ADS9228IRGZR)
- CMOS output interface direct to FPGAs/ASICs (vs ADS9228IRGZR)
Notes de conception
Use separate analog (AGND) and digital (DGND) ground planes joined at a single point beneath the IC. Place the internal reference bypass capacitor (typically 0.1 uF ceramic in parallel with 10 uF tantalum) as close to the REF pin as the layout allows; long traces add noise that directly degrades ADC SNR. Route analog input traces as differential pairs with controlled 100 ohm differential impedance to preserve SNR at full 80 MSPS.
Estimated: the ADC draws ~120 mW per channel at 80 MSPS from a 3.3 V supply (typical figure inferred from datasheet family). Place 0.1 uF ceramic decoupling capacitors on every AVDD pin within 5 mm of the pin and add a 10 uF bulk tantalum near the supply entry point. Use a ferrite bead between analog and digital 3.3 V rails to prevent digital switching noise from coupling into the analog reference.
Keep the CLK trace short and route it away from analog input traces; a 1 cm CLK trace couples switching edges into the analog front end. According to the MaxLinear datasheet, the CLK input is sensitive to jitter and jitter directly reduces SNR - use a low-jitter clock oscillator and add a small series resistor at the CLK pin to dampen reflections if the source impedance is not 50 ohm matched.
Do not leave the CMOS data outputs floating when unused - either tie them to known logic levels through the OEA/OEB output-enable pins or to ground through 100 kohm resistors. Driving the outputs into a capacitive load above the datasheet limit will degrade timing margins and may cause metastability in the downstream FPGA. According to the manufacturer datasheet, the OEA and OEB pins default state at power-up should be verified before system bring-up to avoid bus contention on multi-ADC boards.
According to the MaxLinear datasheet, the digital error correction reduces sparkle codes but does not eliminate sample-to-sample coupling; maintain at least one clock period of settling time between channel-switch events if you are using an external analog mux ahead of the ADC. For multi-ADC synchronization, share the same CLK source and use the CMOS control interface to issue matched RESET commands within one clock cycle across all ADCs.
Informations de conformité
RoHS and REACH compliance per MaxLinear/Exar product page. AEC-Q100 not applicable - this is a commercial/industrial ADC, not an automotive-qualified part. Halogen-free status not explicitly documented in verified web data.
