DS90C385MTD - 85MHz Programmable LVDS Transmitter | Texas Instruments
Référence : DS90C385MTD ✗ Fin de vieDS90C385MTD Présentation
An LVDS transmitter is a physical-layer interface IC that converts low-voltage digital logic into a balanced differential signal. The differential architecture is commonly used to transport data reliably over cable or PCB traces while limiting electromagnetic interference, reducing sensitivity to ground noise, and enabling higher data rates than ordinary single-ended logic. Within the interface hierarchy, this device is an LVDS line driver and serializer for display links.
The DS90C385MTD is associated with an 85 MHz FPD-Link interface, a +3.3 V supply, programmable operation, and a 56-pin TSSOP package. The verified distributor records describe it as a four-driver LVDS transmitter for flat panel display links. Its parallel-to-differential conversion function makes it suitable for carrying compact digital video or control data between a graphics controller and a display or another LVDS endpoint.
This family also appears under the DS90C365 description, which identifies the device as an 18-bit or 24-bit FPD-Link transmitter operating at 85 MHz. Different DS90C365 and DS90C385 family members can differ in supported data width, enable controls, and implementation details, so engineers must confirm the exact pin configuration and electrical limits against the manufacturer datasheet before substituting a related MPN.
Typical applications include digital flat-panel display interfaces, industrial monitor links, video timing and control paths, and other point-to-point systems where LVCMOS logic must be converted to differential LVDS. The 56-pin TSSOP package provides enough pins for dedicated differential data, clock, control, configuration, and power connections while supporting standard board-level assembly.
A successful implementation requires careful review of supply voltage, input and output levels, pin functions, termination, trace geometry, and decoupling. Differential pairs should be routed with controlled spacing and matched length, while power and ground connections should be kept quiet. The verified search results do not provide a public pin table or detailed electrical limits, so those values must be confirmed in the manufacturer datasheet before layout or production use.
This product record combines verified distributor metadata, package and application context, available replacement information, and practical selection guidance. It also distinguishes documented facts from parameters that still require datasheet confirmation, helping engineers evaluate the DS90C385MTD without relying on unverified assumptions.
Alternatives de remplacement direct pour DS90C385MTD — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
DS90C386MTD
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
DS90C385AMT
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
DS90C385AMT/NOPB
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
DS90C385A
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
DS90C385MTDX
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
DS90C385MTD Spécifications
| Product Type | Programmable LVDS Transmitter |
| Tension d'alimentation | +3.3 V |
| Operating Frequency | 85 MHz |
| Data Configuration | 24-bit FPD-Link |
| Alternate Data Configuration | 18-bit FPD-Link |
| Input Logic | LVCMOS/LVTTL |
| Output Logic | Differential LVDS |
| Input Data Width | 28 bits |
| Driver Count | 4 drivers |
| Receiver Count | 0 receivers |
| Boîtier | 56-pin TSSOP |
| Package Type | Standard gull-wing CMOS TSSOP |
| Maximum Supply Voltage | 3.6 V |
| Minimum Operating Temperature | 0 °C |
| Maximum Operating Temperature | 70 °C |
| Programmability | Programmable |
| Statut RoHS | Non-RoHS Compliant |
Guide de configuration des broches du DS90C385MTD standard gull-wing cmos tssop
Configuration des broches du DS90C385MTD (boîtier standard gull-wing cmos tssop). La numérotation des broches, les fonctions et les schémas de connexion sont définis dans la fiche technique du fabricant. Consultez-la pour l'empreinte exacte et les directives de soudage.
Aucune donnée de brochage détaillée disponible pour DS90C385MTD.
Consultez la fiche technique pour la configuration complète des broches.
Applications typiques
DS90C385MTD convient pour 6 applications: Digital Flat-Panel Display Interface, Industrial Monitor Data Link, Video Timing Control Path, Point-to-Point Embedded Display Link, Digital Signage Controller Interface, Test and Measurement Front Panel.
Digital Flat-Panel Display Interface
The DS90C385MTD fits a digital flat-panel display link because it converts parallel LVCMOS or LVTTL data into differential LVDS at an 85 MHz FPD-Link rate. Its four-driver structure allows multiple display data lanes to leave a graphics controller over balanced connections, reducing susceptibility to common-mode noise compared with single-ended signaling. The 56-pin TSSOP footprint supports separate data, clock, control, configuration, power, and ground connections. Before routing, engineers should confirm the exact pin table and lane assignment in the manufacturer datasheet and preserve matched differential geometry to maintain signal integrity.
Recommandé
Industrial Monitor Data Link
The DS90C385MTD can support an industrial monitor data link where a controller drives display information over a cable or a longer PCB connection. Differential LVDS is useful in industrial environments because its balanced signal helps reject noise coupled equally onto both conductors. The verified +3.3 V supply and 85 MHz FPD-Link operation align with compact embedded display architectures. However, the source data indicates a 0 °C to 70 °C range, so wider-temperature industrial deployments need additional qualification, along with verified EMC, grounding, and connector requirements.
Recommandé
Video Timing Control Path
The DS90C385MTD is suitable for transporting timing and control information from a display timing controller when the destination accepts differential LVDS. Its 28-bit parallel input path and four LVDS drivers provide multiple lanes for organized point-to-point data transfer at 85 MHz. Using differential outputs can improve noise immunity and simplify common-mode termination planning compared with single-ended routing. The design should reserve equal input and output return-path geometry, keep clock and data lane skew within device requirements, and verify all enable and configuration levels against the exact manufacturer datasheet.
Recommandé
Point-to-Point Embedded Display Link
An embedded processor or programmable logic device can use the DS90C385MTD as a parallel-to-LVDS interface for a remote display subsystem. The transmitter accepts conventional LVCMOS or LVTTL signaling and generates differential LVDS outputs, allowing the board or cable connection to operate more reliably in electrically noisy equipment. At the 85 MHz FPD-Link rate, layout quality remains critical: keep the differential pairs short where possible, avoid splitting return planes beneath the pairs, and use the manufacturer-recommended termination network. Firmware should also verify supported width and configuration modes.
Recommandé
Digital Signage Controller Interface
The DS90C385MTD can provide the physical link between a digital-signage controller and an LVDS-capable display assembly. Four differential drivers support organized multi-lane transmission, while the 85 MHz operating point suits established flat-panel display timing. Balanced LVDS reduces radiated-noise and ground-offset sensitivity in multi-panel installations compared with single-ended driver outputs. System integrators should verify cable length, connector pinout, input-video format, and panel refresh requirements because those system parameters are not contained in the supplied device records and cannot be inferred from the transmitter's FPD-Link description.
Recommandé
Test and Measurement Front Panel
The DS90C385MTD may be used in test or measurement equipment that drives a remote display, status panel, or visualization node over a balanced LVDS connection. Its 85 MHz operation and four-output arrangement permit several data lanes to cross a controlled cable or board interface while retaining better common-noise immunity than single-ended logic. For a front-panel implementation, validate display timing, connector ground references, isolation strategy, and ESD requirements. The verified record does not provide full timing or power-consumption values, so the complete manufacturer datasheet remains necessary for signal-integrity and thermal calculations.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour DS90C385MTD — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | DS90C386MTD | DS90C385AMT | DS90C385AMT/NOPB | DS90C385A | DS90C385MTDX |
|---|---|---|---|---|---|---|
| Package | 56-pin TSSOP | 56-pin TSSOP | 56-pin TSSOP | 56-pin TSSOP | 56-pin TSSOP | 56-pin TSSOP |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Product Type | Programmable LVDS Transmitter | LVDS Transmitter | LVDS Transmitter | LVDS Transmitter | LVDS Transmitter | LVDS Transmitter |
| Drop-In Status | Original device | Direct pin-to-pin alternative | Pin-to-pin compatible DS90C385-family device | Pin-to-pin compatible DS90C385A-family device | Pin-to-pin compatible successor-family variant | Functionally similar X-suffix variant |
Principaux différenciateurs
- Directly documented pin-to-pin replacement path (vs DS90C386MTD)
- Compatible A-family upgrade path (vs DS90C385AMT)
- Established 85 MHz FPD-Link application profile (vs DS90CR285MTD/NOPB)
Notes de conception
Route each LVDS output as a controlled-impedance differential pair with tightly matched spacing and approximately matched length. Avoid splitting the ground or power plane beneath a pair, and minimize stubs from test pads or connector transitions. The verified records establish an 85 MHz FPD-Link interface but do not provide the manufacturer trace-geometry table, so the final stack-up and routing values must be taken from the official datasheet and the connected receiver's requirements.
Validate the complete transmitter-to-receiver channel rather than treating the DS90C385MTD outputs as isolated logic signals. Confirm differential impedance, connector or cable loss, receiver termination, clock-to-data skew, and allowed lane skew using the manufacturer timing and AC specifications. The available data does not include rise time, differential voltage, jitter, or maximum data-rate values, making those missing datasheet parameters essential to any first-pass SI budget.
Decouple the +3.3 V supply close to the device using the capacitance and connection recommendations in the manufacturer datasheet. Keep the supply return path continuous and separate noisy switching-current paths from the transmitter and display interface. Because the supplied records do not state typical or maximum supply current, power dissipation, output loading, or the logic input levels, do not size the supply or estimate thermal rise until those values are obtained from the complete datasheet.
Do not substitute a related DS90C385 or DS90C385A MPN solely because its package matches. Confirm configuration pins, enable polarity, clock behavior, supported data width, supply limits, temperature grade, and output mapping. The verified cross-reference data identifies DS90C386MTD as a direct pin-to-pin alternative and the DS90C385A family as compatible, but related family members can still differ in programming details or features that affect board operation.
Informations de conformité
The verified Chip and IC listing identifies DS90C385MTD as non-RoHS compliant. No verified REACH, lead-free, halogen-free, AEC-Q100, or conflict-minerals declarations were supplied.
