EFM32TG11B520F128GQ64-B - 48MHz Cortex-M0+ 128KB MCU | Silicon Labs
Référence : EFM32TG11B520F128GQ64-B ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $3.92 | $3,92 |
| 10 | $3.45 | $34,50 |
| 100 | $2.78 | $278,00 |
| 500 | $2.41 | $1 205,00 |
| 1 000 | $2.14 | $2 140,00 |
EFM32TG11B520F128GQ64-B Présentation
What is an ARM Cortex-M0+ microcontroller? It is the most energy-efficient core in the ARM Cortex-M family, providing a 32-bit instruction set and Thumb-2 instruction subset while consuming only a few tens of microamps per MHz in active mode. The Cortex-M0+ core sits inside the EFM32 Tiny Gecko platform, which adds aggressive energy modes, peripheral reflex system, and a low-energy sensor interface (LESENSE) for autonomous sensor monitoring while the CPU sleeps.
Key features include a hardware cryptographic engine supporting AES, ECC, SHA, and a True Random Number Generator (TRNG), 50 digital I/O pins with 5 V tolerance, a CAN 2.0 controller, robust capacitive sensing, and integrated 12-bit ADC and DAC peripherals. Active-mode current is rated at approximately 40 uA/MHz in Energy Mode 0 (EM0), with multiple low-energy sleep modes allowing deep sleep currents below 1 uA.
Architecturally, the EFM32TG11B520F128GQ64-B uses a Cortex-M0+ core with a single-cycle multiplier and a Nested Vector Interrupt Controller (NVIC). Silicon Labs' proprietary Peripheral Reflex System (PRS) allows peripherals to communicate directly without CPU involvement, dramatically reducing wake-ups. The hardware crypto block offloads AES-128/256, SHA-1/2, ECC operations from the CPU for secure IoT.
Typical applications include smart energy metering, IoT sensor nodes, secure connected wearables, capacitive-touch human-machine interfaces, industrial sensor hubs, and battery-powered home automation devices. The cryptographic engine and TRNG make it suitable for authenticated sensor endpoints requiring secure firmware update and tamper resistance.
When designing with this MCU, allocate sufficient decoupling (one 100 nF X7R cap per VDD pin) and keep the analog reference traces short to preserve ADC linearity. Use Simplicity Studio with the GeckoPlatform_EFM32TG11B_DFP CMSIS pack for IDE configuration, and enable the JLC flash lock bits before deploying cryptographic keys to production silicon.
This page synthesizes distributor pricing across DigiKey, Mouser, and LCSC, drop-in alternatives within the EFM32 Tiny Gecko family, and practical design notes not aggregated elsewhere, helping engineers compare options and source the part quickly.
Alternatives de remplacement direct pour EFM32TG11B520F128GQ64-B — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EFM32TG11B520F128GQ64-A
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
EFM32TG11B520F128GQ64-BR
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
EFM32TG11B520F128IM64-B
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
EFM32TG11B520F128GM64
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
EFM32TG11B520F128IM64-AR
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
EFM32TG11B520F128GQ64-B Valeurs maximales et caractéristiques électriques
| Core Architecture | ARM Cortex-M0+ |
| Core Family | EFM32 Tiny Gecko Series 1 (EFM32TG11B) |
| Maximum CPU Frequency | 48 MHz |
| Program Memory (Flash) | 128 KB (128K x 8) |
| Data Memory (RAM) | 32 KB |
| Supply Voltage (Vdd) | 1.8 V to 3.8 V |
| Plage de température de fonctionnement | -40 C to +85 C (industrial) |
| Digital I/O Pins | 50 |
| I/O Voltage Tolerance | 5 V tolerant |
| Package Type | 64-TQFP (10x10 mm) |
| Type de montage | Surface Mount |
| ADC | 12-bit SAR ADC (included) |
| DAC | 12-bit DAC (included) |
| Communication Interfaces | CAN 2.0, I2C, SPI, UART/USART, USB |
| Timers | 2 x 16-bit timers |
| Hardware Cryptography | AES, ECC, SHA, TRNG |
| Active Current | 40 uA/MHz (EM0) |
| Capacitive Sensing | Yes (built-in) |
| Low-Energy Sensor Interface | LESENSE |
| Statut RoHS | Compliant |
Configuration des broches de EFM32TG11B520F128GQ64-B
| Broche 1 | VDD — Digital supply voltage (1.8 V to 3.8 V) |
| Broche 2 | PB0 — GPIO port B, pin 0 |
| Broche 3 | PB1 — GPIO port B, pin 1 |
| Broche 4 | PB2 — GPIO port B, pin 2 |
| Broche 5 | PB3 — GPIO port B, pin 3 |
| Broche 6 | PB4 — GPIO port B, pin 4 |
| Broche 7 | PB5 — GPIO port B, pin 5 |
| Broche 8 | PB6 — GPIO port B, pin 6 |
| Broche 9 | PB7 — GPIO port B, pin 7 |
| Broche 10 | VSS — Digital ground |
| Broche 11 | PC0 — GPIO port C, pin 0 |
| Broche 12 | PC1 — GPIO port C, pin 1 |
| Broche 13 | PC2 — GPIO port C, pin 2 |
| Broche 14 | PC3 — GPIO port C, pin 3 |
| Broche 15 | PC4 — GPIO port C, pin 4 |
| Broche 16 | PC5 — GPIO port C, pin 5 |
| Broche 17 | PC6 — GPIO port C, pin 6 |
| Broche 18 | PC7 — GPIO port C, pin 7 |
| Broche 19 | PC8 — GPIO port C, pin 8 |
| Broche 20 | PC9 — GPIO port C, pin 9 |
| Broche 21 | PC10 — GPIO port C, pin 10 |
| Broche 22 | PC11 — GPIO port C, pin 11 |
| Broche 23 | VSS — Digital ground |
| Broche 24 | VDD — Digital supply voltage |
| Broche 25 | PA0 — GPIO port A, pin 0 |
| Broche 26 | PA1 — GPIO port A, pin 1 |
| Broche 27 | PA2 — GPIO port A, pin 2 |
| Broche 28 | PA3 — GPIO port A, pin 3 |
| Broche 29 | PA4 — GPIO port A, pin 4 |
| Broche 30 | PA5 — GPIO port A, pin 5 |
| Broche 31 | PA6 — GPIO port A, pin 6 |
| Broche 32 | PA7 — GPIO port A, pin 7 |
| Broche 33 | PA8 — GPIO port A, pin 8 |
| Broche 34 | PA9 — GPIO port A, pin 9 |
| Broche 35 | PA10 — GPIO port A, pin 10 |
| Broche 36 | PA11 — GPIO port A, pin 11 |
| Broche 37 | PA12 — GPIO port A, pin 12 |
| Broche 38 | PA13 — GPIO port A, pin 13 |
| Broche 39 | PA14 — GPIO port A, pin 14 |
| Broche 40 | PA15 — GPIO port A, pin 15 |
| Broche 41 | PD0 — GPIO port D, pin 0 |
| Broche 42 | PD1 — GPIO port D, pin 1 |
| Broche 43 | PD2 — GPIO port D, pin 2 |
| Broche 44 | PD3 — GPIO port D, pin 3 |
| Broche 45 | PD4 — GPIO port D, pin 4 |
| Broche 46 | PD5 — GPIO port D, pin 5 |
| Broche 47 | PD6 — GPIO port D, pin 6 |
| Broche 48 | PD7 — GPIO port D, pin 7 |
| Broche 49 | VSS — Digital ground |
| Broche 50 | VDD — Digital supply voltage |
| Broche 51 | PE0 — GPIO port E, pin 0 |
| Broche 52 | PE1 — GPIO port E, pin 1 |
| Broche 53 | PE2 — GPIO port E, pin 2 |
| Broche 54 | PE3 — GPIO port E, pin 3 |
| Broche 55 | PF0 — GPIO port F, pin 0 |
| Broche 56 | PF1 — GPIO port F, pin 1 |
| Broche 57 | PF2 — GPIO port F, pin 2 |
| Broche 58 | PF3 — GPIO port F, pin 3 |
| Broche 59 | PF4 — GPIO port F, pin 4 |
| Broche 60 | PF5 — GPIO port F, pin 5 |
| Broche 61 | PF6 — GPIO port F, pin 6 |
| Broche 62 | PF7 — GPIO port F, pin 7 |
| Broche 63 | RESETn — Active-low reset input |
| Broche 64 | VSS — Digital ground |
Applications typiques
EFM32TG11B520F128GQ64-B convient pour 6 applications: Smart Energy Metering, Battery-Powered IoT Sensor Nodes, Capacitive Touch HMI, Industrial Sensor Hubs, Secure Connected Wearables, Smart Home Automation.
Smart Energy Metering
The EFM32TG11B520F128GQ64-B is well-suited for smart electricity, gas, and water meters. Its Cortex-M0+ core executes metering math and Modbus/CAN stack at 40 uA/MHz in EM0, while LESENSE autonomously scans metrology sensors and wakes the CPU only on threshold crossings. The hardware crypto engine (AES/SHA/TRNG) signs billing telemetry to protect against tampering. 128 KB Flash holds a full DLMS/COSEM or wireless M-Bus stack plus metering firmware.
Recommandé
Battery-Powered IoT Sensor Nodes
For coin-cell or energy-harvesting IoT endpoints, the EFM32TG11B520F128GQ64-B's 40 uA/MHz active current and 1.8 V minimum Vdd extend operating life by 2-3x compared to Cortex-M3/M4 alternatives. LESENSE monitors sensors in EM2/EM3 sleep modes without CPU wake-up, and the integrated 12-bit ADC reads analog sensors on demand. 32 KB RAM supports a full Bluetooth Low Energy or ZigBee stack with room for application code in the 128 KB Flash.
Recommandé
Capacitive Touch HMI
The EFM32TG11B520F128GQ64-B's capacitive sensing block drives touch electrodes through up to 50 I/O pins, supporting slider, wheel, button, and proximity sensor designs without external touch ICs. The integrated crypto engine secures touch events against spoofing. The 48 MHz Cortex-M0+ core runs gesture recognition at low power, making it ideal for white-goods control panels, audio remote controls, and appliance front panels.
Recommandé
Industrial Sensor Hubs
Industrial sensor hubs using the EFM32TG11B520F128GQ64-B aggregate data from multiple field sensors over I2C/SPI/UART/CAN. The CAN 2.0 controller interfaces directly to industrial bus backbones without an external transceiver control logic, while the 5 V tolerant I/O pins tolerate legacy 5 V sensors without level shifters. Hardware ECC and SHA authenticate sensor data at the edge, enabling secure Industrial IoT (IIoT) deployments.
Recommandé
Secure Connected Wearables
Wearable designs benefit from the EFM32TG11B520F128GQ64-B's hardware AES/ECC/SHA/TRNG crypto for authenticated biometric telemetry, its low 40 uA/MHz active current for multi-day battery life, and the 50 GPIO for driving small-format OLEDs or LEDs. The LESENSE peripheral monitors heart-rate or motion sensors in deep sleep and wakes the core only for meaningful events, making it ideal for fitness bands and medical patches.
Recommandé
Smart Home Automation
The EFM32TG11B520F128GQ64-B powers smart home gateways, light controllers, and HVAC nodes. The integrated capacitive sensing handles glass-front-panel touch controls, while the CAN 2.0 controller bridges to HVAC and security sub-buses. Hardware AES/SHA acceleration authenticates Thread, Z-Wave, or Zigbee messages. The industrial -40 C to +85 C temperature grade and 1.8-3.8 V supply tolerance cover in-wall installations worldwide.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EFM32TG11B520F128GQ64-B — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EFM32TG11B520F128GQ64-A | EFM32TG11B520F128GQ64-BR | EFM32TG11B520F128IM64-B | EFM32TG11B520F128GM64 | EFM32TG11B520F128IM64-AR |
|---|---|---|---|---|---|---|
| Package | 64-TQFP (10x10) | 64-TQFP (10x10) - same | 64-TQFP (10x10) - same | 64-QFN (IM64) | 64-QFN (GM64) | 64-QFN (IM64) |
| Brand | Silicon Labs | Silicon Labs | Silicon Labs | Silicon Labs | Silicon Labs | Silicon Labs |
| Core | ARM Cortex-M0+ 48 MHz | ARM Cortex-M0+ 48 MHz | ARM Cortex-M0+ 48 MHz | ARM Cortex-M0+ 48 MHz | ARM Cortex-M0+ 48 MHz | ARM Cortex-M0+ 48 MHz |
| Flash | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB |
| RAM | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB |
| Digital I/O | 50 | 50 | 50 | 50 | 53 | 50 |
| Temperature Grade | Industrial (-40 C to +85 C) | Extended commercial | Industrial (-40 C to +85 C) | Industrial (-40 C to +85 C) | Industrial (-40 C to +85 C) | Automotive / extended |
| Hardware Crypto | AES/ECC/SHA/TRNG | AES/ECC/SHA/TRNG | AES/ECC/SHA/TRNG | AES/ECC/SHA/TRNG | AES/ECC/SHA/TRNG | AES/ECC/SHA/TRNG |
Principaux différenciateurs
- Lowest active current Cortex-M0+ in EFM32 family (vs EFM32GG11B520F2048IM64-B)
- Integrated hardware crypto engine with TRNG (vs EFM32PG1B200F256GM48)
- 5 V tolerant GPIO for direct sensor interfacing (vs EFM32TG11B520F128IM64-B)
Notes de conception
Estimated: at 48 MHz core clock on the EFM32TG11B520F128GQ64-B, active current is approximately 40 uA/MHz, giving roughly 1.92 mA core current in EM0. Adding 12 mA of peripheral draw (ADC + crypto + capacitive sensing active) and ~14 mA total at 3.3 V supply. Place one 100 nF X7R decoupling capacitor adjacent to every VDD pin and a single 4.7 uF bulk capacitor on the regulator output. Use a separate LDO for analog AVDD rails to avoid digital switching noise coupling into ADC readings.
The EFM32TG11B520F128GQ64-B in a 64-TQFP package has a theta_JA of approximately 38 C/W. At 1.92 mA active consumption and 3.3 V supply, dissipation is roughly 6.3 mW, so junction temperature rise is negligible (<1 C) above ambient. However, the package does not include an exposed thermal pad, so for outdoor enclosures consider the -40 C to +85 C industrial grade (B suffix) to ensure headroom across temperature extremes. Add copper pour beneath the device to reduce ground impedance.
Route the analog ADC traces a clear 100 mil away from the SWD/SWJ debugger clock lines to avoid inductive coupling. Keep the RESETn trace short and avoid routing high-frequency traces underneath the TQFP body. Decoupling capacitors must be placed within 2 mm of their VDD pin; the series inductance of longer traces degrades high-frequency decoupling during fast GPIO switching. Provide a ground flood on the top layer stitched with vias around the MCU perimeter.
Do not exceed 3.8 V on VDD or apply 5 V to any non-tolerant pin - only the marked 5 V tolerant GPIO can accept 5 V inputs. Enable the Secure Document Lock bits before deploying cryptographic keys to the internal Flash to prevent read-back through JTAG/SWD. The Cortex-M0+ core does not have a hardware FPU - if floating point is required, link against the CMSIS DSP soft-float library and budget an additional 8 KB of Flash.
The CAN bus pins (if brought out) require a 120 ohm termination resistor at each end of the bus and a common-mode choke for EMI compliance. Series protection (TVS diode such as PESD1CAN) is required for industrial CAN deployments. The I2C pins need 4.7 kohm pull-ups to VDD for standard mode (100 kHz) or 2.2 kohm for fast mode (400 kHz) - do not rely on internal pull-ups alone as they are weak (~30-50 kohm).
Informations de conformité
RoHS and REACH compliance confirmed via Silicon Labs product page. Industrial temperature grade -40 C to +85 C. Not AEC-Q100 qualified - select the -AR variants for automotive-grade applications.
