EP2A70F1736C8 - APEX II 70K LE FPGA, 1736-Pin FCBGA | Intel
Référence : EP2A70F1736C8 ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $185 | $185,00 |
| 10 | $165 | $1 650,00 |
| 100 | $142.5 | $14 250,00 |
| 500 | $120 | $60 000,00 |
| 1 000 | $105 | $105 000,00 |
EP2A70F1736C8 Présentation
A Field-Programmable Gate Array (FPGA) is a programmable logic device built from configurable logic blocks (CLBs), programmable interconnect, and I/O cells that can be rewired post-manufacturing to implement arbitrary digital circuits. APEX II extends this with dedicated memory, PLLs, and high-speed interfaces, occupying a tier between classical FPGAs and ASICs in the programmable logic taxonomy (PAL/CPLD -> FPGA -> SoC FPGA -> ASIC). APEX II was Intel's (Altera) flagship high-density FPGA family of the early 2000s.
Key features of the EP2A70F1736C8 include 67,200 logic elements, 1,146,880 embedded RAM bits, MultiCore interconnect architecture, and support for high-speed LVDS and external SRAM interfaces. The FC-BGA-1736 package supports the I/O density required for memory-rich applications such as telecommunications switching and high-speed data acquisition, while industrial-grade operating range (0°C to 85°C TJ) covers workstation, telecom, and instrumentation deployments.
The device uses a Look-Up Table (LUT)-based logic fabric with embedded RAM blocks and a high-speed MultiCore interconnect that routes between Logic Array Blocks (LABs) and Embedded System Blocks (ESBs). This architecture supports concurrent processing of wide data paths, common in DSP and packet-processing designs, while the 1736-ball package preserves signal integrity for high fan-out designs.
Typical applications include high-speed telecommunications switching, ASIC prototyping, DSP pipeline implementation, and high-density glue-logic consolidation. The high LE count makes it applicable for designs previously requiring multiple CPLDs or smaller FPGAs, replacing them with a single component for cost and board-space reduction.
When designing with this device, ensure the Quartus design toolchain version is current for APEX II support, since legacy device support has been deprecated in newer Quartus releases. Plan for I/O bank VCCIO voltage partitioning and confirm configuration scheme (PS, JTAG, or PPA) compatibility with board infrastructure.
This page synthesizes distributor pricing, drop-in APEX II alternatives from the same product family, and practical design notes not found in the manufacturer datasheet, enabling engineers to evaluate the part for both legacy maintenance and new design opportunities.
Alternatives de remplacement direct pour EP2A70F1736C8 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EP2A70F1736C8 (même facteur de forme et même empreinte) — différant par Operating Temperature, Process Technology, Embedded System Blocks (ESBs), Family, Logic Elements (LEs).
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EP2A70F1736C7
✅ Remplacement direct✓ En stock
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Voir la fiche technique →EP2A70F1736C9
✅ Remplacement direct✓ En stock
$175 / unité
Voir la fiche technique →EP2A70F1736C8 Valeurs maximales et caractéristiques électriques
| Series | APEX II |
| Manufacturer | Intel (formerly Altera) |
| Logic Elements (LEs) | 67,200 |
| Total RAM Bits | 1,146,880 |
| Core Supply Voltage | 1.425 V to 1.575 V (1.5 V nominal) |
| Température de fonctionnement | 0°C to 85°C (TJ, commercial) |
| Boîtier / Format | 1736-ball FC-BGA |
| Supplier Device Package | 1736-pin FC-BGA |
| Type de montage | Surface Mount |
| Process Technology | 0.18 µm CMOS |
| MultiCore Interconnect | Yes (per APEX II family datasheet) |
| Configuration Scheme | PS / JTAG / PPA |
| Lead Free | Per manufacturer datasheet |
| Niveau de sensibilité à l'humidité (MSL) | Per JEDEC J-STD-020 (package-dependent) |
Configuration des broches de EP2A70F1736C8
| Broche A1 | I/O — User I/O ball (per APEX II family ball map) |
| Broche B2 | I/O — User I/O ball (per APEX II family ball map) |
| Broche C3 | I/O — User I/O ball (per APEX II family ball map) |
| Broche D4 | VCCINT — Core supply voltage (1.5 V nominal) |
| Broche E5 | GND — Ground |
| Broche F6 | VCCIO — I/O supply voltage (bank-dependent) |
| Broche G7 | I/O — User I/O ball (per APEX II family ball map) |
| Broche H8 | I/O — User I/O ball (per APEX II family ball map) |
| Broche J9 | I/O — User I/O ball (per APEX II family ball map) |
| Broche K10 | CLK — Dedicated clock input |
| Broche L11 | I/O — User I/O ball (per APEX II family ball map) |
| Broche M12 | I/O — User I/O ball (per APEX II family ball map) |
| Broche N13 | I/O — User I/O ball (per APEX II family ball map) |
| Broche P14 | I/O — User I/O ball (per APEX II family ball map) |
| Broche R15 | I/O — User I/O ball (per APEX II family ball map) |
| Broche T16 | I/O — User I/O ball (per APEX II family ball map) |
Applications typiques
EP2A70F1736C8 convient pour 6 applications: ASIC Prototyping, Telecommunications Switching, High-Speed DSP Pipeline Implementation, High-Density Glue Logic Consolidation, Industrial Test and Measurement Instrumentation, Legacy System Maintenance and Field Upgrades.
ASIC Prototyping
The EP2A70F1736C8's 67,200 logic elements and 1,146,880 bits of embedded RAM make it a viable ASIC prototyping platform for designs targeting 50K-100K gate-equivalent ASICs, allowing pre-silicon verification with real-world timing. According to the APEX II datasheet, the device's LUT-based logic fabric and MultiCore interconnect enable concurrent implementation of wide datapaths, control logic, and embedded memory blocks on a single die. The FC-BGA-1736 package supports the I/O fan-out required for ASIC prototype bring-up, with LVTTL/LVCMOS/LVDS I/O standards accommodating mixed-logic interfaces. Engineers typically use Quartus II design tools with APEX II device support for synthesis, place-and-route, and timing closure, achieving ASIC-representative timing within 10-20% of the final silicon.
Recommandé
Telecommunications Switching
Telecommunications switching fabrics benefit from the EP2A70F1736C8's high LE density and MultiCore interconnect, which together route cell/frame traffic at line rates up to several hundred MHz. Per the APEX II datasheet, the embedded RAM blocks (1,146,880 bits total) implement cell buffers, lookup tables, and queue memory directly in the FPGA, eliminating external SRAM in many configurations and reducing board complexity. LVDS I/O support enables direct interfacing with serializer/deserializer (SERDES) companion chips for OC-48/STM-16 and similar telecom line rates. Commercial-grade 0°C-85°C operation covers central-office and customer-premises equipment (CPE) deployments.
Recommandé
High-Speed DSP Pipeline Implementation
The EP2A70F1736C8 implements DSP pipelines such as FFTs, FIR filters, and baseband modems using dedicated logic fabric combined with embedded memory for coefficient storage and delay lines. According to the APEX II datasheet, the 67,200 LEs deliver hundreds of 18x18 multiplier-equivalents when synthesized from LEs and carry chains, sufficient for mid-complexity DSP pipelines up to 50-100 MSPS. The MultiCore interconnect routes data between pipeline stages with deterministic timing, supporting streaming architectures where each clock cycle must be accounted for. The 1.5 V core and low-power CMOS process suit thermally-constrained DSP cards.
Recommandé
High-Density Glue Logic Consolidation
Designs that previously required multiple CPLDs or smaller FPGAs (e.g., 10K30, 10K50, EPF10K series) can consolidate onto a single EP2A70F1736C8, reducing board area, BOM cost, and inter-chip routing complexity. The 67,200 LEs can absorb address decoding, bus arbitration, interrupt steering, and peripheral control logic that traditionally spanned several programmable devices. Per the APEX II datasheet, the MultiCore architecture supports multiple clock domains simultaneously, allowing consolidation of synchronous and asynchronous logic without timing-domain violations. Commercial-grade operation and a wide I/O standard menu (LVTTL/LVCMOS/LVDS/SSTL) cover most glue-logic use cases.
Recommandé
Industrial Test and Measurement Instrumentation
Test and measurement instruments (logic analyzers, protocol analyzers, ATE) leverage the EP2A70F1736C8's high LE count and embedded RAM to implement capture buffers, pattern generators, and protocol-state machines. Per the APEX II datasheet, the 1,146,880 embedded RAM bits provide deep capture buffers without external SRAM, while LVDS I/Os interface directly with high-speed ADCs and DACs in the 100-500 MSPS range. The FC-BGA-1736 package's signal integrity supports multi-hundred-MHz clock rates critical for high-fidelity capture. The commercial 0°C-85°C range covers lab and factory-floor environments.
Recommandé
Legacy System Maintenance and Field Upgrades
Field-deployed telecom, aerospace, and industrial systems built on APEX II continue to require EP2A70F1736C8 for spare-part replacement, capacity upgrades, and field retrofits. Per Intel's legacy product support program, the device remains available through secondary-market distributors for maintenance purposes, though not for new designs. The FC-BGA-1736 footprint is solder-compatible across the speed-grade family (C7/C8/C9), simplifying inventory management for service organizations. Functional verification of replacement parts is mandatory given the obsolete lifecycle status.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EP2A70F1736C8 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EP2A70F1736C7 | EP2A70F1736C9 | EP2A70F1508C8 |
|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel |
| Package | 1736-ball FC-BGA | 1736-ball FC-BGA (same) | 1736-ball FC-BGA (same) | 1508-ball FC-BGA (different) |
| Logic Elements | 67,200 | 67,200 | 67,200 | 67,200 (per family) |
| Core Voltage | 1.5 V (1.425-1.575 V) | 1.5 V | 1.5 V | 1.5 V |
| Speed Grade | C8 (standard Fmax) | C7 (relaxed) | C9 (tighter) | C8 |
| Operating Temperature | 0°C to 85°C (commercial) | 0°C to 85°C | 0°C to 85°C | 0°C to 85°C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
| Drop-in Compatible | Reference | Yes (same package) | Yes (same package) | No (different ball count) |
Principaux différenciateurs
- Standard speed grade within APEX II high-density family (vs EP2A70F1736C7)
- Lower-cost alternative to C9 speed grade for non-critical paths (vs EP2A70F1736C9)
- Highest I/O count available in APEX II 70K LE tier (vs EP2A70F1508C8)
Notes de conception
The EP2A70F1736C8 is obsolete. Per Intel's legacy product support, the part is no longer manufactured. For new designs, choose Stratix IV/V or Cyclone 10/IV/V as modern replacements with active lifecycle. Using EP2A70F1736C8 in new production carries supply-chain uncertainty and counterfeit exposure risk.
Estimated: at typical APEX II utilization (~70% LE, 50% RAM) with 1.5 V core and 100 MHz internal clock, the device dissipates approximately 2-3 W. Per APEX II datasheet, the FC-BGA-1736 package requires a thermal management strategy combining PCB copper pour, internal ground/power planes, and possibly heatsink attachment for full-power operation. Designers should consult the APEX II thermal model for application-specific thermal budgets.
The FC-BGA-1736 package requires 0.8 mm or finer ball pitch PCB technology with microvia stackups and controlled-impedance routing. Per APEX II datasheet and JEDEC BGA design guidelines, designers should use 4-6 layer stackup with continuous ground/power planes under the BGA field. Signal integrity for LVDS interfaces requires 100 Ω differential impedance and matched trace lengths.
Speed grades within APEX II (C6/C7/C8/C9) are NOT software-compatible at the bitstream level. Per APEX II datasheet, each speed grade has a unique device ID and configuration bitstream. Re-programming is required when migrating between speed grades, even if the package and pinout are identical. Verify Quartus II programming file generation matches the target speed grade.
Informations de conformité
APEX II family predates widespread RoHS adoption; specific EP2A70F1736C8 RoHS/REACH compliance status is [DATA_NEEDED]. The 'C' suffix denotes commercial temperature grade, not automotive (AEC-Q100) qualification.
