LAN8770RT-I - 100BASE-T1 Single-Pair Ethernet PHY | Microchip
Référence : LAN8770RT-I ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $0 | $0,00 |
| 10 | $0 | $0,00 |
| 100 | $0 | $0,00 |
| 500 | $0 | $0,00 |
| 1 000 | $0 | $0,00 |
LAN8770RT-I Présentation
A single-pair Ethernet (SPE) PHY is a physical-layer device that converts the digital MAC-layer signals of a media access controller into analog signals suitable for transmission over twisted-pair cabling. Within the network hierarchy - MAC, PHY, transformer, connector - the PHY occupies the layer that determines compliance with physical-layer standards. The LAN8770 complies with the IEEE 802.3bw-2015 (100BASE-T1) automotive Ethernet specification, supporting cable lengths of up to at least 15 meters over a single unshielded twisted pair.
Key features include full MII and RMII media-independent interfaces for connection to a wide range of MACs and microcontrollers, a 1.1 V core supply domain, 4/4 driver/receiver configuration, and industrial temperature operation from -40C to +85C. The wettable-flank QFN package supports reliable solder-joint inspection in automotive-grade assembly processes, and the exposed pad provides low-impedance thermal and ground paths.
Technically, the LAN8770 integrates the analog front end, ADC/DSP-based equalization, echo cancellation, and clock recovery required for robust single-pair signaling per IEEE 802.3bw-2015. Because 100BASE-T1 uses full-duplex transmission on one pair rather than two pairs as in 100BASE-TX, hybrid echo cancellation is a critical block, and Microchip's DSP architecture addresses this while keeping the bill of materials compact.
Typical applications include automotive camera and sensor links, ECU-to-ECU in-vehicle networking, industrial PROFINET-style single-pair field links, and compact IoT gateways where four-wire cabling is unnecessary. The RMII interface makes it a natural companion to NXP, STMicroelectronics, and Microchip MCUs.
When designing, pay close attention to the 1.1 V core supply sequencing and the magnetics-free single-pair link termination, which differs from conventional 100BASE-TX designs. The exposed pad must be soldered to a solid ground pour for thermal and EMI performance.
This page synthesizes verified distributor data, compliance details, pricing availability guidance, and design notes not found in the manufacturer datasheet, providing engineers with a single citable reference.
Alternatives de remplacement direct pour LAN8770RT-I — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
Aucune alternative de remplacement direct disponible pour ce produit.
Demander des alternativesLAN8770RT-I Spécifications
| Protocol | Ethernet (100BASE-T1) |
| Standards Compliance | IEEE 802.3bw-2015 |
| Débit de données | 100 Mbps |
| Interface | MII, RMII |
| Number of Drivers/Receivers | 4/4 |
| Tension d'alimentation | 1.1 V |
| Cable Type | Single Unshielded Twisted Pair (UTP) |
| Supported Cable Length | Up to at least 15 m |
| Ports | 1 |
| Température de fonctionnement | -40C to +85C |
| Boîtier | 36-VQFN (6x6 mm), Exposed Pad, Wettable Flank |
| Type de montage | Surface Mount |
| Niveau de sensibilité à l'humidité (MSL) | 3 (168 Hours) |
| ECCN | EAR99 |
| HTSUS | 8542.39.0001 |
| REACH Status | REACH Unaffected |
| Statut RoHS | Compliant |
Guide de configuration des broches du LAN8770RT-I 36-vqfn (6x6 mm), exposed pad, wettable flank
Configuration des broches du LAN8770RT-I (boîtier 36-vqfn (6x6 mm), exposed pad, wettable flank). La numérotation des broches, les fonctions et les schémas de connexion sont définis dans la fiche technique du fabricant. Consultez-la pour l'empreinte exacte et les directives de soudage.
Aucune donnée de brochage détaillée disponible pour LAN8770RT-I.
Consultez la fiche technique pour la configuration complète des broches.
Applications typiques
LAN8770RT-I convient pour 6 applications: Automotive Camera Links, ECU-to-ECU In-Vehicle Networking, Industrial Single-Pair Field Links, IoT Gateways and Edge Nodes, Sensor Aggregation Nodes, Test and Measurement Adapters.
Automotive Camera Links
The LAN8770RT-I is well suited to automotive camera links because 100BASE-T1 over a single unshielded twisted pair provides 100 Mbit/s full-duplex bandwidth sufficient for compressed video streams from surround-view, rear-view, and driver-monitoring cameras, in a package (36-VQFN 6x6 mm) small enough to sit inside compact camera modules. Compliance with IEEE 802.3bw-2015 guarantees interoperability with automotive switch and gateway silicon. The -40C to +85C Grade 1 operating range and wettable-flank package meet automotive assembly and inspection requirements. In the signal chain, the camera-side serializer or MCU connects to the LAN8770 through its RMII interface using a single 50 MHz reference clock, while the single UTP pair carries both transmit and receive traffic via integrated echo cancellation. Designers should budget harness length within the supported 15-meter reach and validate EMI performance of the unshielded pair in the vehicle environment.
Recommandé
ECU-to-ECU In-Vehicle Networking
For ECU-to-ECU communication, the LAN8770RT-I enables lightweight 100BASE-T1 point-to-point links between body, chassis, and domain controllers without the cost and weight of a full multi-port switch or four-pair cabling. The single UTP pair carries 100 Mbit/s full-duplex traffic across harness segments of up to at least 15 meters, matching the majority of in-vehicle point-to-point runs, and IEEE 802.3bw-2015 compliance ensures coexistence with higher-speed 1000BASE-T1 backbone links. The MII/RMII host interfaces connect directly to the Ethernet MAC embedded in automotive MCUs such as the SPC5 and S912 families, requiring only a 50 MHz reference in RMII mode. Its Grade 1 temperature rating (-40C to +85C), RoHS compliance, and EAR99 classification simplify qualification and export. Designers should follow Microchip's reference termination for the single-pair link and verify bit-error rate on the production harness, since unshielded pairs are sensitive to coupling from adjacent high-current harnesses.
Recommandé
Industrial Single-Pair Field Links
In industrial automation, the LAN8770RT-I brings single-pair Ethernet economics to field-level devices such as sensors, drives, and I/O modules that traditionally relied on RS-485 or multi-pair Ethernet. The 100 Mbit/s full-duplex rate over one UTP pair, at lengths up to at least 15 meters (extendable with 100BASE-T1-compliant cabling practice), provides ample bandwidth for deterministic I/O protocols running over standard IP stacks. The RMII interface attaches directly to industrial MCUs and FPGAs, and the compact 6x6 mm VQFN fits inside dense I/O modules and miniature sensor housings. Although the industrial plant floor can exceed the -40C to +85C specification near hot equipment, the range covers most cabinet and machine-mounted installations. The wettable-flank package supports AOI in high-reliability assembly. Engineers should isolate the field pair with proper termination networks per the Microchip datasheet and evaluate EMC performance against plant-floor noise, since the 100BASE-T1 link is unshielded by definition.
Recommandé
IoT Gateways and Edge Nodes
Compact IoT gateways benefit from the LAN8770RT-I's combination of a small 36-VQFN (6x6 mm) footprint, low component count, and standard MII/RMII connectivity. A gateway MCU with an RMII-capable MAC attaches to the LAN8770 with a single 50 MHz clock, and the PHY's 100 Mbit/s single-pair link backhauls data from the edge node to an aggregation switch without requiring a four-pair cable run - valuable in building automation, smart-metering clusters, and retrofit installations where existing single-pair or thin cabling is reused. The 1.1 V core supply keeps active power low, extending the thermal budget of passively cooled enclosures, and operation from -40C to +85C covers unconditioned outdoor cabinets. Because 100BASE-T1 is designed for point-to-point links, the topology should be star-shaped from a switch or higher-layer gateway. Designers should also verify supply sequencing of the multi-rail PHY architecture against the Microchip datasheet to avoid latch-up during hot-plug events.
Recommandé
Sensor Aggregation Nodes
The LAN8770RT-I fits sensor aggregation nodes where multiple low-bandwidth sensors (lidar preprocessing boards, radar front ends, IMU clusters) funnel data to a central controller over a single 100 Mbit/s pair. The PHY's RMII interface offers a small pin-count connection to the aggregation MCU, while the 100BASE-T1 link provides enough headroom to carry aggregated, timestamped sensor frames with Ethernet's built-in time-sync support (with a suitable PTP-capable MAC). The 6x6 mm package allows mounting directly on the sensor headboard, and the exposed pad supplies a low-impedance ground reference that helps contain EMI from the PHY's analog front end in dense multi-board assemblies. The -40C to +85C range and RoHS/wettable-flank construction satisfy automotive sensor qualification flows. Cable runs should stay within the supported at-least-15-meter reach, and designers should include common-mode choke and termination networks per Microchip's reference design to meet in-vehicle or industrial EMC limits on the unshielded pair.
Recommandé
Test and Measurement Adapters
Engineering teams building 100BASE-T1 test adapters, compliance fixtures, and diagnostics tools use the LAN8770RT-I as a reference PHY because it implements the full IEEE 802.3bw-2015 signal set, allowing a PC or instrument to attach to a device-under-test's single-pair link. The MII interface exposes raw frame access for protocol analyzers, while the RMII mode suits FPGA-based capture platforms needing deterministic timing. The 36-VQFN (6x6 mm) package with wettable flanks is straightforward to place on small adapter boards, and the exposed ground pad supports the clean grounding required for accurate transmit-level and return-loss measurements. Because test adapters frequently hot-plug into unknown link partners, engineers should implement robust supply sequencing and ESD protection on the single-pair port, following Microchip's application guidance. The -40C to +85C range easily covers bench and chamber testing, and RoHS compliance keeps fixtures compliant with internal environmental policies.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour LAN8770RT-I — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | LAN8700C-AEZG |
|---|---|---|
| Package | 36-VQFN (6x6 mm), Exposed Pad, Wettable Flank | 32-QFN - NOT the same package (not drop-in) |
| Brand | Microchip Technology | Microchip Technology |
| Physical Layer Standard | 100BASE-T1 (IEEE 802.3bw-2015), single UTP pair | 10/100BASE-TX, two twisted pairs |
| Data Rate | 100 Mbps | 10/100 Mbps |
| Host Interface | MII, RMII | MII, RMII |
| Operating Temperature | -40C to +85C | -40C to +85C |
| Supported Cable Length | Up to at least 15 m (single pair) | Up to 100 m (two pairs, typical 100BASE-TX) |
Principaux différenciateurs
- Single-pair 100BASE-T1 compliance (vs LAN8700C-AEZG)
- Automotive-oriented package construction (vs LAN8700C-AEZG)
- Dual MII/RMII host flexibility (vs LAN8700C-AEZG)
Notes de conception
Solder the exposed pad of the 36-VQFN (6x6 mm) package to a continuous ground pour with an array of thermal vias. The exposed pad is the primary ground return for the PHY's analog front end and the main thermal path; an unsoldered or poorly wetted pad commonly causes both EMI failures and intermittent link errors. The wettable flanks allow AOI verification of side-fillet formation, so design the solder-mask openings to enable visible fillets at assembly. Note this guidance is general VQFN practice; follow the LAN8770 datasheet layout section for the exact landing pattern.
The LAN8770 uses a 1.1 V core supply domain per distributor technical data, in addition to I/O and analog rails detailed in the datasheet. Decouple each supply pin with a 100 nF capacitor placed within 2 mm of the pin, plus bulk capacitance per the reference design. Verify power-up sequencing between rails before layout freeze, since multi-rail PHYs can latch up if I/O domains are powered ahead of the core. Estimated power dissipation is modest at 100 Mbps, but confirm with the datasheet's supply current figures for your exact mode (MII vs RMII, auto-negotiation state).
The 100BASE-T1 link is full-duplex on a single unshielded pair, so echo cancellation performance depends heavily on the external termination network and magnetics/transformer selection specified by Microchip. Keep the PHY-to-connector pair as a tightly coupled 100-ohm differential route, avoid stubs, and place the common-mode choke and termination components exactly as shown in the Microchip reference design. Since cable reach is specified to at least 15 m, validate bit-error rate on the actual production harness, especially in vehicles where the pair runs adjacent to switched high-current loads.
Informations de conformité
RoHS compliant and REACH Unaffected per distributor technical data (exchips, sourced from DigiKey parameter data). ECCN EAR99; HTSUS 8542.39.0001; MSL 3 (168 hours). AEC-Q100 qualification status was not stated in the retrieved data - the product brief describes a Grade 1 temperature variant; consult Microchip for formal qualification documents.
