LTC2155CUP-12 - Dual 12-Bit 170Msps ADC | Analog Devices
Référence : LTC2155CUP-12 ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $65.2 | $65,20 |
| 10 | $62.52 | $625,20 |
| 100 | $56.1 | $5 610,00 |
| 500 | $49.8 | $24 900,00 |
| 1 000 | $44.25 | $44 250,00 |
LTC2155CUP-12 Présentation
What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed ADC architecture that breaks the conversion into multiple low-resolution stages, each handling one sample per clock cycle. This pipeline approach enables high sampling rates (hundreds of Msps) while maintaining moderate resolution (10-16 bits), making pipelined ADCs the standard for communications, radar, and instrumentation applications. The LTC2155 belongs to the dual-pipelined ADC category, integrating two matched ADC channels on a single die for I/Q baseband or diversity reception.
Key features of the LTC2155CUP-12 include a 1.25 GHz full-power bandwidth sample-and-hold, an optional clock duty cycle stabilizer, low-power sleep and nap modes, and a serial SPI port for configuration. The pin-compatible 14-bit versions (LTC2157-14/LTC2156-14/LTC2155-14) allow easy migration when higher dynamic range is needed. The differential inputs are easy to drive, simplifying front-end design for direct-IF sampling receivers.
The architecture uses a high-speed pipelined core with on-chip reference and sample-and-hold, achieving excellent linearity and low jitter. DDR LVDS outputs simplify data capture by providing one data pair per channel per clock edge, reducing the number of data lines routed on the PCB. The internal duty cycle stabilizer compensates for clock source imperfections, preserving SNR at high input frequencies.
Typical applications include communications receivers, cellular base stations, radar and LiDAR signal chains, portable instrumentation, medical imaging front-ends, and software-defined radio (SDR) platforms. The combination of dual channels, low power, and small QFN-64 footprint makes the LTC2155CUP-12 particularly suited to multi-channel compact systems.
When designing with this ADC, pay close attention to the analog input network: a differential transformer or driver amplifier must present 1.5 V peak-to-peak to maximize SNR. Use low-jitter clock sources and matched-length differential output pairs to preserve LVDS timing margins at 170 Msps.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
Alternatives de remplacement direct pour LTC2155CUP-12 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec LTC2155CUP-12 (même facteur de forme et même empreinte) — différant par Package, SNR, RoHS Status, Sampling Rate, Operating Temperature Range.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
LTC2155IUP-12#PBF
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
LTC2156CUP-12#PBF
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
LTC2157CUP-12#PBF
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
LTC2155CUP-12#TRPBF
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
LTC2145CUP-12
✅ Remplacement direct✓ En stock
$26.4 / unité
Voir la fiche technique →LTC2155CUP-12 Valeurs maximales et caractéristiques électriques
| Résolution | 12 bits |
| Number of Channels | 2 (dual) |
| Fréquence d'échantillonnage | 170 Msps |
| Architecture | Pipelined |
| SNR | 68.5 dB |
| SFDR | 90 dB |
| Tension d'alimentation | 1.8 V (single) |
| Power Consumption | 545 mW |
| Input Type | Differential |
| Input Range | 1.5 V peak-to-peak |
| Full-Power Bandwidth | 1.25 GHz |
| Output Interface | DDR LVDS |
| Boîtier | QFN-64 (UP) 9 mm × 9 mm |
| Configuration Interface | Serial SPI |
| Plage de température de fonctionnement | Commercial (0C to +70C) |
Configuration des broches de LTC2155CUP-12
| Broche 1 | AIN1+ — Channel 1 positive differential analog input |
| Broche 2 | AIN1- — Channel 1 negative differential analog input |
| Broche 3 | VCM1 — Channel 1 common-mode voltage output |
| Broche 4 | GND — Ground |
| Broche 5 | AIN2+ — Channel 2 positive differential analog input |
| Broche 6 | AIN2- — Channel 2 negative differential analog input |
| Broche 7 | VCM2 — Channel 2 common-mode voltage output |
| Broche 8 | GND — Ground |
| Broche 9 | AVDD1.8 — 1.8V analog supply |
| Broche 10 | AVDD1.8 — 1.8V analog supply |
| Broche 11 | GND — Ground |
| Broche 12 | REF — Internal reference decoupling |
| Broche 13 | REFT — Differential reference top |
| Broche 14 | REFB — Differential reference bottom |
| Broche 15 | GND — Ground |
| Broche 16 | AVDD1.8 — 1.8V analog supply |
| Broche 17 | GND — Ground |
| Broche 18 | AVDD1.8 — 1.8V analog supply |
| Broche 19 | GND — Ground |
| Broche 20 | CLK+ — Clock input positive |
| Broche 21 | CLK- — Clock input negative |
| Broche 22 | GND — Ground |
| Broche 23 | CS — SPI chip select |
| Broche 24 | SCK — SPI serial clock |
| Broche 25 | SDI — SPI serial data input |
| Broche 26 | SDO — SPI serial data output |
| Broche 27 | OVDD — LVDS output supply |
| Broche 28 | OGND — LVDS output ground |
| Broche 29 | NC — Not connected |
| Broche 30 | OUT1A+ — Channel 1 LVDS output A positive |
| Broche 31 | OUT1A- — Channel 1 LVDS output A negative |
| Broche 32 | OUT1B+ — Channel 1 LVDS output B positive |
| Broche 33 | OUT1B- — Channel 1 LVDS output B negative |
| Broche 34 | OVDD — LVDS output supply |
| Broche 35 | OGND — LVDS output ground |
| Broche 36 | OUTCLK+ — LVDS output clock positive |
| Broche 37 | OUTCLK- — LVDS output clock negative |
| Broche 38 | OUTFR+ — LVDS frame output positive |
| Broche 39 | OUTFR- — LVDS frame output negative |
| Broche 40 | OGND — LVDS output ground |
| Broche 41 | OVDD — LVDS output supply |
| Broche 42 | OUT2A+ — Channel 2 LVDS output A positive |
| Broche 43 | OUT2A- — Channel 2 LVDS output A negative |
| Broche 44 | OUT2B+ — Channel 2 LVDS output B positive |
| Broche 45 | OUT2B- — Channel 2 LVDS output B negative |
| Broche 46 | OVDD — LVDS output supply |
| Broche 47 | OGND — LVDS output ground |
| Broche 48 | MODE — Mode select pin |
| Broche 49 | NAP — Nap mode pin |
| Broche 50 | SLEEP — Sleep mode pin |
| Broche 51 | RST — Reset pin |
| Broche 52 | GND — Ground |
| Broche 53 | AVDD1.8 — 1.8V analog supply |
| Broche 54 | GND — Ground |
| Broche 55 | AVDD1.8 — 1.8V analog supply |
| Broche 56 | GND — Ground |
| Broche 57 | AVDD1.8 — 1.8V analog supply |
| Broche 58 | GND — Ground |
| Broche 59 | AVDD1.8 — 1.8V analog supply |
| Broche 60 | AVDD1.8 — 1.8V analog supply |
| Broche 61 | GND — Ground |
| Broche 62 | DCS — Duty cycle stabilizer enable |
| Broche 63 | OVDD — LVDS output supply |
| Broche 64 | OGND — LVDS output ground |
Applications typiques
LTC2155CUP-12 convient pour 6 applications: Cellular Base Station Receiver, Radar and LiDAR Signal Chains, Portable Test and Measurement Instrumentation, Software Defined Radio (SDR) Platforms, Medical Imaging Front-Ends, Industrial Process Control and Data Acquisition.
Cellular Base Station Receiver
The LTC2155CUP-12's dual 12-bit 170 Msps channels and 68.5 dB SNR suit multi-carrier cellular base-station digitizers where two diversity antennas feed a single ADC. The 1.5 V peak-to-peak differential input range simplifies coupling from a passive IF transformer without a front-end amplifier, while DDR LVDS outputs ease timing closure into a baseband FPGA or ASIC. At 545 mW total, the part enables compact, multi-channel receivers in macro and small-cell BTS designs.
Recommandé
Radar and LiDAR Signal Chains
Wide dynamic range demands in radar and LiDAR front-ends map directly to the LTC2155CUP-12's 90 dB SFDR and 1.25 GHz full-power bandwidth. The dual channels digitize I/Q baseband returns simultaneously with matched latency, preserving phase coherence for Doppler and FMCW processing. Low power (545 mW) and a 9×9 mm QFN footprint allow dense multi-channel arrays in phased-array radar modules.
Recommandé
Portable Test and Measurement Instrumentation
Portable oscilloscopes and spectrum analyzers benefit from the LTC2155CUP-12's 170 Msps dual channels, low 545 mW power, and small QFN-64 footprint. Battery-powered instruments can digitize two channels simultaneously while preserving SNR at high input frequencies via the 1.25 GHz analog bandwidth. The integrated SPI port simplifies per-channel gain and offset calibration in production test fixtures.
Recommandé
Software Defined Radio (SDR) Platforms
SDR platforms demand flexible, dual-channel ADCs with low noise and moderate sample rates - exactly the LTC2155CUP-12's 68.5 dB SNR / 90 dB SFDR / 170 Msps profile. The single 1.8 V supply simplifies power design on USB-powered dongles and embedded SDR boards, while DDR LVDS outputs stream data into FPGAs (e.g., Xilinx Artix, Lattice ECP5) used for DSP. The dual channels capture I/Q baseband directly from quadrature demodulators.
Recommandé
Medical Imaging Front-Ends
Ultrasound and other medical imaging systems use multi-channel ADC arrays for beamforming. The LTC2155CUP-12's dual matched channels fit dense channel layouts, while 68.5 dB SNR preserves dynamic range required for tissue contrast. Low power (545 mW) keeps per-channel thermal load manageable in handheld or cart-based systems where patient safety and battery life are priorities.
Recommandé
Industrial Process Control and Data Acquisition
Multi-axis industrial controllers and high-speed data acquisition cards use the LTC2155CUP-12 to digitize vibration, position, and control-loop feedback. The dual channels allow simultaneous sampling of paired sensors (e.g., current and voltage, or X-Y axis position) with matched latency. Industrial LVDS runs reliably in electrically noisy factory environments, while the SPI port allows per-channel configuration during operation.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour LTC2155CUP-12 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | LTC2155IUP-12#PBF | LTC2156CUP-12#PBF | LTC2157CUP-12#PBF | LTC2145CUP-12 |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | QFN-64 (UP) 9x9 mm | QFN-64 (UP) 9x9 mm - same | QFN-64 (UP) 9x9 mm - same | QFN-64 (UP) 9x9 mm - same | QFN-64 (UP) 9x9 mm - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Sampling Rate | 170 Msps | 170 Msps | 210 Msps | 250 Msps | 125 Msps |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Power Consumption | 545 mW | 545 mW | 592 mW | 628 mW | 420 mW |
| SNR | 68.5 dB | 68.5 dB | 67.5 dB | 65.5 dB | 70 dB |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) |
Principaux différenciateurs
- Lowest power in the LTC2157/LTC2156/LTC2155 12-bit family (vs LTC2157CUP-12#PBF)
- Industrial temperature grade alternative available in same package (vs LTC2155IUP-12#PBF)
- Higher SNR than faster family members due to lower speed grade (vs LTC2157CUP-12#PBF)
- Higher sampling than slower LTC2145 family for wideband use (vs LTC2145CUP-12)
Notes de conception
Use a solid ground plane on layer 2 with the QFN-64 exposed pad soldered to a continuous copper pour that connects to the analog ground. Keep analog input traces impedance-controlled at 100 ohm differential, route them as short as possible, and avoid crossing any digital LVDS lines. Place 0.1uF ceramic bypass capacitors within 2 mm of every AVDD1.8 pin and a 10uF bulk capacitor near the reference pin.
Drive the LTC2155CUP-12 CLK+/CLK- input with a low-jitter, differential clock source (typical 50% duty cycle, <300fs RMS jitter) to preserve SNR at high input frequencies. Enable the on-chip duty cycle stabilizer (DCS pin high) when the external clock duty cycle deviates from 50%, which compensates for duty-cycle distortion and prevents SNR degradation at high input frequencies approaching Nyquist.
Use a linear LDO (such as LT3042 or LT3080) to derive the 1.8V AVDD supply from a 3.3V rail to avoid switching noise coupling into the analog input. Add a ferrite bead and additional 10uF + 0.1uF decoupling between the LDO and the AVDD pin. Separate the OVDD (LVDS supply) plane from the AVDD plane and stitch with a single-point bridge to prevent digital switching noise from corrupting the analog reference.
Route the four LVDS data pairs (OUT1A, OUT1B, OUT2A, OUT2B), the LVDS output clock (OUTCLK), and the LVDS frame (OUTFR) as 100 ohm differential traces with matched lengths (within 1 ps skew, or approximately 150 um). Maintain continuous ground beneath each LVDS pair, avoid 90 degree bends, and use controlled impedance stack-up. Series-terminate each LVDS output near the ADC with 100 ohm differential impedance to prevent reflections.
Informations de conformité
RoHS compliant per ADI product page ordering suffix #PBF. AEC-Q100 not qualified - choose automotive-grade LTC2155AUP or industrial LTC2155IUP-12 variants for harsher environments. Halogen-free status not stated in the verified datasheet snippet - confirm with ADI customer support for halogen-free specific orders.
