LTC2155CUP-12 - Dual 12-Bit 170Msps ADC | Analog Devices
MPN： LTC2155CUP-12 ✓ 啟用中LTC2155CUP-12 概覽
What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed ADC architecture that breaks the conversion into multiple low-resolution stages, each handling one sample per clock cycle. This pipeline approach enables high sampling rates (hundreds of Msps) while maintaining moderate resolution (10-16 bits), making pipelined ADCs the standard for communications, radar, and instrumentation applications. The LTC2155 belongs to the dual-pipelined ADC category, integrating two matched ADC channels on a single die for I/Q baseband or diversity reception.
Key features of the LTC2155CUP-12 include a 1.25 GHz full-power bandwidth sample-and-hold, an optional clock duty cycle stabilizer, low-power sleep and nap modes, and a serial SPI port for configuration. The pin-compatible 14-bit versions (LTC2157-14/LTC2156-14/LTC2155-14) allow easy migration when higher dynamic range is needed. The differential inputs are easy to drive, simplifying front-end design for direct-IF sampling receivers.
The architecture uses a high-speed pipelined core with on-chip reference and sample-and-hold, achieving excellent linearity and low jitter. DDR LVDS outputs simplify data capture by providing one data pair per channel per clock edge, reducing the number of data lines routed on the PCB. The internal duty cycle stabilizer compensates for clock source imperfections, preserving SNR at high input frequencies.
Typical applications include communications receivers, cellular base stations, radar and LiDAR signal chains, portable instrumentation, medical imaging front-ends, and software-defined radio (SDR) platforms. The combination of dual channels, low power, and small QFN-64 footprint makes the LTC2155CUP-12 particularly suited to multi-channel compact systems.
When designing with this ADC, pay close attention to the analog input network: a differential transformer or driver amplifier must present 1.5 V peak-to-peak to maximize SNR. Use low-jitter clock sources and matched-length differential output pairs to preserve LVDS timing margins at 170 Msps.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
直接替換替代品，適用於 LTC2155CUP-12 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： LTC2155CUP-12 （相同外形與佔位） — 差異在於 Package, SNR, RoHS Status, Sampling Rate, Operating Temperature Range.
LTC2155IUP-12#PBF
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2156CUP-12#PBF
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2157CUP-12#PBF
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2155CUP-12#TRPBF
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2145CUP-12
✅ 直接替換聯絡詢價
查看資料表 →LTC2155CUP-12 最大額定值與電氣特性
| 解析度 | 12 bits |
| Number of Channels | 2 (dual) |
| 取樣率 | 170 Msps |
| Architecture | Pipelined |
| SNR | 68.5 dB |
| SFDR | 90 dB |
| 供應電壓 | 1.8 V (single) |
| Power Consumption | 545 mW |
| Input Type | Differential |
| Input Range | 1.5 V peak-to-peak |
| Full-Power Bandwidth | 1.25 GHz |
| Output Interface | DDR LVDS |
| 封裝 | QFN-64 (UP) 9 mm × 9 mm |
| Configuration Interface | Serial SPI |
| 工作溫度範圍 | Commercial (0C to +70C) |
LTC2155CUP-12 腳位配置
| 腳位 1 | AIN1+ — Channel 1 positive differential analog input |
| 腳位 2 | AIN1- — Channel 1 negative differential analog input |
| 腳位 3 | VCM1 — Channel 1 common-mode voltage output |
| 腳位 4 | GND — Ground |
| 腳位 5 | AIN2+ — Channel 2 positive differential analog input |
| 腳位 6 | AIN2- — Channel 2 negative differential analog input |
| 腳位 7 | VCM2 — Channel 2 common-mode voltage output |
| 腳位 8 | GND — Ground |
| 腳位 9 | AVDD1.8 — 1.8V analog supply |
| 腳位 10 | AVDD1.8 — 1.8V analog supply |
| 腳位 11 | GND — Ground |
| 腳位 12 | REF — Internal reference decoupling |
| 腳位 13 | REFT — Differential reference top |
| 腳位 14 | REFB — Differential reference bottom |
| 腳位 15 | GND — Ground |
| 腳位 16 | AVDD1.8 — 1.8V analog supply |
| 腳位 17 | GND — Ground |
| 腳位 18 | AVDD1.8 — 1.8V analog supply |
| 腳位 19 | GND — Ground |
| 腳位 20 | CLK+ — Clock input positive |
| 腳位 21 | CLK- — Clock input negative |
| 腳位 22 | GND — Ground |
| 腳位 23 | CS — SPI chip select |
| 腳位 24 | SCK — SPI serial clock |
| 腳位 25 | SDI — SPI serial data input |
| 腳位 26 | SDO — SPI serial data output |
| 腳位 27 | OVDD — LVDS output supply |
| 腳位 28 | OGND — LVDS output ground |
| 腳位 29 | NC — Not connected |
| 腳位 30 | OUT1A+ — Channel 1 LVDS output A positive |
| 腳位 31 | OUT1A- — Channel 1 LVDS output A negative |
| 腳位 32 | OUT1B+ — Channel 1 LVDS output B positive |
| 腳位 33 | OUT1B- — Channel 1 LVDS output B negative |
| 腳位 34 | OVDD — LVDS output supply |
| 腳位 35 | OGND — LVDS output ground |
| 腳位 36 | OUTCLK+ — LVDS output clock positive |
| 腳位 37 | OUTCLK- — LVDS output clock negative |
| 腳位 38 | OUTFR+ — LVDS frame output positive |
| 腳位 39 | OUTFR- — LVDS frame output negative |
| 腳位 40 | OGND — LVDS output ground |
| 腳位 41 | OVDD — LVDS output supply |
| 腳位 42 | OUT2A+ — Channel 2 LVDS output A positive |
| 腳位 43 | OUT2A- — Channel 2 LVDS output A negative |
| 腳位 44 | OUT2B+ — Channel 2 LVDS output B positive |
| 腳位 45 | OUT2B- — Channel 2 LVDS output B negative |
| 腳位 46 | OVDD — LVDS output supply |
| 腳位 47 | OGND — LVDS output ground |
| 腳位 48 | MODE — Mode select pin |
| 腳位 49 | NAP — Nap mode pin |
| 腳位 50 | SLEEP — Sleep mode pin |
| 腳位 51 | RST — Reset pin |
| 腳位 52 | GND — Ground |
| 腳位 53 | AVDD1.8 — 1.8V analog supply |
| 腳位 54 | GND — Ground |
| 腳位 55 | AVDD1.8 — 1.8V analog supply |
| 腳位 56 | GND — Ground |
| 腳位 57 | AVDD1.8 — 1.8V analog supply |
| 腳位 58 | GND — Ground |
| 腳位 59 | AVDD1.8 — 1.8V analog supply |
| 腳位 60 | AVDD1.8 — 1.8V analog supply |
| 腳位 61 | GND — Ground |
| 腳位 62 | DCS — Duty cycle stabilizer enable |
| 腳位 63 | OVDD — LVDS output supply |
| 腳位 64 | OGND — LVDS output ground |
典型應用
LTC2155CUP-12 適用於 6 應用s: Cellular Base Station Receiver, Radar and LiDAR Signal Chains, Portable Test and Measurement Instrumentation, Software Defined Radio (SDR) Platforms, Medical Imaging Front-Ends, Industrial Process Control and Data Acquisition.
Cellular Base Station Receiver
The LTC2155CUP-12's dual 12-bit 170 Msps channels and 68.5 dB SNR suit multi-carrier cellular base-station digitizers where two diversity antennas feed a single ADC. The 1.5 V peak-to-peak differential input range simplifies coupling from a passive IF transformer without a front-end amplifier, while DDR LVDS outputs ease timing closure into a baseband FPGA or ASIC. At 545 mW total, the part enables compact, multi-channel receivers in macro and small-cell BTS designs.
推薦
Radar and LiDAR Signal Chains
Wide dynamic range demands in radar and LiDAR front-ends map directly to the LTC2155CUP-12's 90 dB SFDR and 1.25 GHz full-power bandwidth. The dual channels digitize I/Q baseband returns simultaneously with matched latency, preserving phase coherence for Doppler and FMCW processing. Low power (545 mW) and a 9×9 mm QFN footprint allow dense multi-channel arrays in phased-array radar modules.
推薦
Portable Test and Measurement Instrumentation
Portable oscilloscopes and spectrum analyzers benefit from the LTC2155CUP-12's 170 Msps dual channels, low 545 mW power, and small QFN-64 footprint. Battery-powered instruments can digitize two channels simultaneously while preserving SNR at high input frequencies via the 1.25 GHz analog bandwidth. The integrated SPI port simplifies per-channel gain and offset calibration in production test fixtures.
推薦
Software Defined Radio (SDR) Platforms
SDR platforms demand flexible, dual-channel ADCs with low noise and moderate sample rates - exactly the LTC2155CUP-12's 68.5 dB SNR / 90 dB SFDR / 170 Msps profile. The single 1.8 V supply simplifies power design on USB-powered dongles and embedded SDR boards, while DDR LVDS outputs stream data into FPGAs (e.g., Xilinx Artix, Lattice ECP5) used for DSP. The dual channels capture I/Q baseband directly from quadrature demodulators.
推薦
Medical Imaging Front-Ends
Ultrasound and other medical imaging systems use multi-channel ADC arrays for beamforming. The LTC2155CUP-12's dual matched channels fit dense channel layouts, while 68.5 dB SNR preserves dynamic range required for tissue contrast. Low power (545 mW) keeps per-channel thermal load manageable in handheld or cart-based systems where patient safety and battery life are priorities.
推薦
Industrial Process Control and Data Acquisition
Multi-axis industrial controllers and high-speed data acquisition cards use the LTC2155CUP-12 to digitize vibration, position, and control-loop feedback. The dual channels allow simultaneous sampling of paired sensors (e.g., current and voltage, or X-Y axis position) with matched latency. Industrial LVDS runs reliably in electrically noisy factory environments, while the SPI port allows per-channel configuration during operation.
推薦
推薦產品摘要
工程參考資料，適用於 LTC2155CUP-12 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | LTC2155IUP-12#PBF | LTC2156CUP-12#PBF | LTC2157CUP-12#PBF | LTC2145CUP-12 |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | QFN-64 (UP) 9x9 mm | QFN-64 (UP) 9x9 mm - same | QFN-64 (UP) 9x9 mm - same | QFN-64 (UP) 9x9 mm - same | QFN-64 (UP) 9x9 mm - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Sampling Rate | 170 Msps | 170 Msps | 210 Msps | 250 Msps | 125 Msps |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Power Consumption | 545 mW | 545 mW | 592 mW | 628 mW | 420 mW |
| SNR | 68.5 dB | 68.5 dB | 67.5 dB | 65.5 dB | 70 dB |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) |
主要差異化特點
- Lowest power in the LTC2157/LTC2156/LTC2155 12-bit family (對比LTC2157CUP-12#PBF)
- Industrial temperature grade alternative available in same package (對比LTC2155IUP-12#PBF)
- Higher SNR than faster family members due to lower speed grade (對比LTC2157CUP-12#PBF)
- Higher sampling than slower LTC2145 family for wideband use (對比LTC2145CUP-12)
設計說明
Use a solid ground plane on layer 2 with the QFN-64 exposed pad soldered to a continuous copper pour that connects to the analog ground. Keep analog input traces impedance-controlled at 100 ohm differential, route them as short as possible, and avoid crossing any digital LVDS lines. Place 0.1uF ceramic bypass capacitors within 2 mm of every AVDD1.8 pin and a 10uF bulk capacitor near the reference pin.
Drive the LTC2155CUP-12 CLK+/CLK- input with a low-jitter, differential clock source (typical 50% duty cycle, <300fs RMS jitter) to preserve SNR at high input frequencies. Enable the on-chip duty cycle stabilizer (DCS pin high) when the external clock duty cycle deviates from 50%, which compensates for duty-cycle distortion and prevents SNR degradation at high input frequencies approaching Nyquist.
Use a linear LDO (such as LT3042 or LT3080) to derive the 1.8V AVDD supply from a 3.3V rail to avoid switching noise coupling into the analog input. Add a ferrite bead and additional 10uF + 0.1uF decoupling between the LDO and the AVDD pin. Separate the OVDD (LVDS supply) plane from the AVDD plane and stitch with a single-point bridge to prevent digital switching noise from corrupting the analog reference.
Route the four LVDS data pairs (OUT1A, OUT1B, OUT2A, OUT2B), the LVDS output clock (OUTCLK), and the LVDS frame (OUTFR) as 100 ohm differential traces with matched lengths (within 1 ps skew, or approximately 150 um). Maintain continuous ground beneath each LVDS pair, avoid 90 degree bends, and use controlled impedance stack-up. Series-terminate each LVDS output near the ADC with 100 ohm differential impedance to prevent reflections.
合規資訊
RoHS compliant per ADI product page ordering suffix #PBF. AEC-Q100 not qualified - choose automotive-grade LTC2155AUP or industrial LTC2155IUP-12 variants for harsher environments. Halogen-free status not stated in the verified datasheet snippet - confirm with ADI customer support for halogen-free specific orders.
