LTC2164CUK - 16-Bit 105Msps Low Power ADC | Analog Devices
Référence : LTC2164CUK ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $38.5 | $38,50 |
| 10 | $34.65 | $346,50 |
| 100 | $30.8 | $3 080,00 |
| 500 | $27.5 | $13 750,00 |
| 1 000 | $24.75 | $24 750,00 |
LTC2164CUK Présentation
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous analog waveform and produces a discrete multi-bit digital representation. Pipelined ADCs, the family to which the LTC2164CUK belongs, use a multi-stage sub-ADC/MDAC/flash architecture to achieve 14-16 bit resolution at tens to hundreds of mega-samples per second while keeping per-stage hardware costs manageable. Within the broader taxonomy, the LTC2164CUK sits at: ADC -> pipelined ADC -> data converter -> mixed-signal IC -> semiconductor. Pipelined parts are the dominant choice for communications infrastructure, defense electronics and high-end instrumentation where 16-bit dynamic range at IF frequencies is mandatory.
Key features of the LTC2164CUK include a single 1.8 V analog supply (with separate digital output supply rail for flexible interfacing), selectable CMOS, DDR CMOS or LVDS output modes, a serial SPI port for mode configuration, integrated shutdown and nap power-save modes, and AC performance that targets demanding communications front-end applications. The part accepts single-ended or differential analog inputs and provides an integrated input common-mode bias network, reducing the external component count on the front-end anti-alias filter.
The LTC2164CUK uses a switched-capacitor pipelined core calibrated at the Analog Devices factory. Internal error-correction logic and digital post-processing yield consistent 76.8 dB SNR and 90 dB SFDR across the IF band of interest. Designers typically pair it with a low-jitter ADC clock buffer (e.g. AD9516 or HMC7044) and a bandpass anti-alias filter. Differential transformer coupling (e.g. ADT1-1WT or Mini-Circuits ADT2-1T) is the standard input configuration to preserve second-order distortion performance.
Typical applications for the LTC2164CUK include wireless base-station receivers, LTE/UMTS and CDMA digitizing IF stages, radar and electronic-warfare intermediate-frequency sampling, broadband software-defined radio (SDR), cable-headend downstream digitizers, and high-end medical imaging front ends. The combination of 16-bit resolution and 105 Msps throughput also makes it useful in scientific test instrumentation and ultrasonic nondestructive testing.
A key design consideration with the LTC2164CUK is clock jitter. Although the part's 0.07 psRMS aperture jitter is exceptionally low, total system SNR is dominated by the analog input frequency multiplied by external clock jitter. Designers should budget at least 0.5 ps of clock-source jitter for IF inputs above 70 MHz, and use a dedicated clock distribution buffer or PLL to keep the sampling edge clean. The exposed pad of the QFN-48 must be soldered to a continuous low-impedance ground plane for thermal and electrical performance.
This page synthesizes distributor stock and pricing, drop-in pin-compatible alternatives, and practical PCB layout notes that supplement the official Analog Devices datasheet family.
Alternatives de remplacement direct pour LTC2164CUK — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec LTC2164CUK (même facteur de forme et même empreinte) — différant par Architecture, Package, Resolution, Analog Supply Voltage, Aperture Jitter.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
LTC2165CUK
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$58.53 / unité
Voir la fiche technique →LTC2163CUK
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
LTC2260IUK
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
LTC2259IUK
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
LTC2151CUJ-14
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$29.1 / unité
Voir la fiche technique →LTC2164CUK Valeurs maximales et caractéristiques électriques
| Résolution | 16 bits |
| Sample Rate (max) | 105 Msps |
| Number of Channels | 1 |
| Converter Type | Pipelined ADC |
| Input Type | Single-ended or differential analog |
| Analog Supply Voltage | 1.8 V (typ) |
| Digital Output Supply | Selectable, compatible with CMOS/LVDS interface |
| Output Interface | CMOS, DDR CMOS, or LVDS (selectable) |
| SNR | 76.8 dB |
| SFDR | 90 dB |
| Aperture Jitter | 0.07 psRMS |
| Configuration Interface | Serial SPI port |
| Power-Save Modes | Shutdown and nap modes |
| Boîtier | 48-pin QFN (7x7) with exposed pad |
| Type de montage | Surface Mount |
| Statut RoHS | Compliant (Pb-free #PBF suffix) |
| Temperature Grade | Commercial |
| Architecture | Switched-capacitor pipelined, factory-calibrated |
Configuration des broches de LTC2164CUK
| Broche 1 | GND — Ground |
| Broche 2 | AINA+ — Differential analog input, positive |
| Broche 3 | AINA- — Differential analog input, negative |
| Broche 4 | VCM — Common-mode voltage for analog input |
| Broche 5 | REFT — Internal reference top, decouple to ground |
| Broche 6 | REFB — Internal reference bottom, decouple to ground |
| Broche 7 | VREF — Internal reference voltage, decouple to ground |
| Broche 8 | SENSE — Reference mode sense input |
| Broche 9 | OGND — Output buffer ground |
| Broche 10 | OVDD — Output supply voltage |
| Broche 11 | D0+ — Digital output bit 0, positive |
| Broche 12 | D0- — Digital output bit 0, negative (LVDS pair) |
| Broche 13 | D1+ — Digital output bit 1, positive |
| Broche 14 | D1- — Digital output bit 1, negative (LVDS pair) |
| Broche 15 | D2+ — Digital output bit 2, positive |
| Broche 16 | D2- — Digital output bit 2, negative (LVDS pair) |
| Broche 17 | D3+ — Digital output bit 3, positive |
| Broche 18 | D3- — Digital output bit 3, negative (LVDS pair) |
| Broche 19 | D4+ — Digital output bit 4, positive |
| Broche 20 | D4- — Digital output bit 4, negative (LVDS pair) |
| Broche 21 | D5+ — Digital output bit 5, positive |
| Broche 22 | D5- — Digital output bit 5, negative (LVDS pair) |
| Broche 23 | D6+ — Digital output bit 6, positive |
| Broche 24 | D6- — Digital output bit 6, negative (LVDS pair) |
| Broche 25 | D7+ — Digital output bit 7, positive |
| Broche 26 | D7- — Digital output bit 7, negative (LVDS pair) |
| Broche 27 | D8+ — Digital output bit 8, positive |
| Broche 28 | D8- — Digital output bit 8, negative (LVDS pair) |
| Broche 29 | D9+ — Digital output bit 9, positive |
| Broche 30 | D9- — Digital output bit 9, negative (LVDS pair) |
| Broche 31 | D10+ — Digital output bit 10, positive |
| Broche 32 | D10- — Digital output bit 10, negative (LVDS pair) |
| Broche 33 | D11+ — Digital output bit 11, positive |
| Broche 34 | D11- — Digital output bit 11, negative (LVDS pair) |
| Broche 35 | D12+ — Digital output bit 12, positive |
| Broche 36 | D12- — Digital output bit 12, negative (LVDS pair) |
| Broche 37 | D13+ — Digital output bit 13, positive |
| Broche 38 | D13- — Digital output bit 13, negative (LVDS pair) |
| Broche 39 | D14+ — Digital output bit 14, positive |
| Broche 40 | D14- — Digital output bit 14, negative (LVDS pair) |
| Broche 41 | D15+ — Digital output bit 15, positive (MSB) |
| Broche 42 | D15- — Digital output bit 15, negative (LVDS pair) |
| Broche 43 | ENC+ — Encode (sample clock) input, positive |
| Broche 44 | ENC- — Encode (sample clock) input, negative |
| Broche 45 | VDD — Analog supply voltage 1.8 V |
| Broche 46 | CS — SPI chip select (active low) |
| Broche 47 | SDI — SPI serial data input |
| Broche 48 | SCK — SPI serial clock |
| Broche EP | Exposed Pad (GND) — Thermal/ground pad, solder to PCB ground plane |
Applications typiques
LTC2164CUK convient pour 6 applications: Wireless Base Station Receiver IF Sampling, Radar and Electronic Warfare IF Digitizer, Broadband Software Defined Radio (SDR), Cable Headend Downstream Digitizer, High-End Medical Imaging Front End, Scientific Test and Measurement Instrumentation.
Wireless Base Station Receiver IF Sampling
The LTC2164CUK's 16-bit resolution, 105 Msps throughput and 0.07 psRMS aperture jitter make it ideally suited for digitizing intermediate-frequency signals inside LTE, UMTS and CDMA base-station receivers. The part supports undersampling of IF frequencies up to several hundred MHz with 76.8 dB SNR and 90 dB SFDR, ensuring that small-signal information above the noise floor is preserved for downstream channelization. A typical signal chain places the LTC2164CUK after a 2nd-IF bandpass filter and a 1:1 RF transformer for differential drive, clocked from a low-jitter source such as AD9516. Unlike an FPGA-based decimator at the same node, this ADC converts directly to digital at the IF, simplifying timing closure and eliminating analog BB stages.
Recommandé
Radar and Electronic Warfare IF Digitizer
The combination of 76.8 dB SNR, 0.07 psRMS aperture jitter and 90 dB SFDR allows the LTC2164CUK to undersample intermediate-frequency radar returns directly, preserving target amplitude information across a wide instantaneous bandwidth. Pin compatibility with the 48-pin 7x7 QFN package family lets system designers reuse a single ADC layout across multiple speed grades (LTC2163/LTC2164/LTC2165) for subsystem scalability. Differential transformer drive at the analog input preserves second-harmonic distortion performance below -90 dBc. Compared with lower-jitter discrete track-and-hold plus flash solutions, the integrated ADC simplifies thermal management and reduces parts count on the RF/IF board, which is especially valuable in size-constrained EW payload applications.
Recommandé
Broadband Software Defined Radio (SDR)
In broadband software-defined radio platforms the LTC2164CUK digitizes wideband RF/IF signals directly to baseband, offloading filtering and demodulation to an FPGA or DSP. Its selectable CMOS, DDR CMOS or LVDS digital output modes support direct connection to modern FPGAs with 1.8 V LVDS I/O, removing the need for external level translators. The integrated SPI configuration port allows real-time trade-off between output mode, gain and shutdown settings under software control. The 120 mW typical power consumption at 105 Msps keeps thermal rise modest in outdoor or backpack SDR enclosures. This flexibility makes the LTC2164CUK a foundation block in tactical, public-safety and engineering SDR products.
Recommandé
Cable Headend Downstream Digitizer
Cable-TV headend receivers require 16-bit dynamic range to capture hundreds of QAM channels to within 0.5 dB amplitude accuracy, and the LTC2164CUK's 76.8 dB SNR and 90 dB SFDR meet this goal at IF sample rates up to 105 Msps. Its integrated input common-mode bias network reduces external component count on the front-end diplexer/AGC network, while the CMOS/LVDS outputs let the headend modulator cluster use 1.8 V FPGA logic. Compared with dual-channel ADCs the LTC2164CUK's single-channel architecture simplifies thermal layout on densely populated line-card designs. The exposed-pad QFN package provides a low-thermal-resistance path for headend chassis with limited airflow.
Recommandé
High-End Medical Imaging Front End
In ultrasound, CT and MRI receiver chains, the LTC2164CUK's 16-bit resolution and 105 Msps throughput allow direct digitization of beamformed RF signals at the probe handle or front-end card. The 76.8 dB SNR provides the dynamic range required to resolve small tissue echoes next to strong specular reflections, while the 0.07 psRMS aperture jitter supports IF undersampling for tighter sub-array footprints. Pin compatibility across the LTC2163/2164/2165 family allows a single PCB to scale with channel count or sample-rate requirements. The configurable SPI port lets field engineers adjust power-versus-bandwidth modes during calibration without altering the BOM.
Recommandé
Scientific Test and Measurement Instrumentation
Wide-bandwidth oscilloscopes, spectrum analyzers and arbitrary waveform digitizers all rely on 16-bit data converters to push dynamic range past legacy 12-14 bit front ends. The LTC2164CUK's pipelined architecture and 0.07 psRMS aperture jitter allow direct IF sampling of signals up to several hundred MHz, replacing traditional analog-downconvert sections with a more compact digital-IF stage. Pin compatibility across the 7x7 QFN-family lets designers reuse the same analog front-end PCB for multiple speed grades (LTC2163/2164/2165). The exposed-pad package keeps thermal rise modest at full 105 Msps operation, an important consideration in densely populated bench-instrument chassis with constrained airflow.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour LTC2164CUK — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | LTC2165CUK | LTC2163CUK | LTC2260IUK | LTC2259IUK | LTC2151CUJ-14 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 48-pin QFN (7x7) with exposed pad | 48-pin QFN (7x7) - same | 48-pin QFN (7x7) - same | 48-pin QFN (7x7) - same | 48-pin QFN (7x7) - same | 48-pin QFN (7x7) - same |
| Resolution | 16 bit | 16 bit | 16 bit | 14 bit | 14 bit | 14 bit |
| Maximum Sample Rate | 105 Msps | 125 Msps | 80 Msps | 125 Msps | 80 Msps | 40 Msps |
| Output Interface | CMOS, DDR CMOS, LVDS | CMOS, DDR CMOS, LVDS | CMOS, DDR CMOS, LVDS | CMOS, DDR CMOS, LVDS | CMOS, DDR CMOS, LVDS | CMOS, DDR CMOS, LVDS |
Principaux différenciateurs
- Mid-speed 105 Msps throughput places it between 80 Msps LTC2163 and 125 Msps LTC2165 in the same family, allowing designers to tune speed/cost without PCB changes (vs LTC2163CUK)
- 76.8 dB SNR and 90 dB SFDR are identical to the LTC2165CUK and LTC2163CUK, so 105 Msps is the sweet spot for price-per-Msps in this family (vs LTC2260IUK)
- 0.07 psRMS aperture jitter supports undersampling of IF frequencies above 200 MHz with negligible SNR penalty (vs LTC2163CUK)
Notes de conception
Estimated SNR loss due to external clock jitter scales as 20*log10(2*pi*f_analog*jitter_ext). For a 95 MHz IF input and an external clock jitter of 1 psRMS the SNR penalty is approximately 54.6 dB, well above the ADC's intrinsic 76.8 dB SNR. Always budget a clock source and clock buffer with sub-0.3 psRMS jitter when the analog input frequency exceeds 70 MHz, otherwise the system's effective SNR will be dominated by the clock rather than the ADC.
Estimated: route the differential AINA+/AINA- and ENC+/ENC- inputs with 100 ohm differential impedance and length-matched traces within 2 mm of each other. Place a 0.1 uF X7R ceramic bypass capacitor within 1-2 mm of each VDD and OVdd pin, and a bulk 4.7 uF tantalum or polymer capacitor within 5 mm of the analog supply rail. The QFN exposed pad must be soldered directly to a continuous, low-inductance ground plane for thermal dissipation and electrical ground integrity.
Estimated: isolate the analog (AIN, REFT, REFB, VREF, VCM) and digital (Dxx, OVDD, OGND) grounds and merge them at a single point, typically directly under the part's exposed pad. Separating the analog and digital grounds prevents digital switching noise from coupling into the analog input, which would otherwise degrade SFDR by 10-15 dB. Additionally, keep the SPI configuration traces (CS, SDI, SCK) away from the parallel LVDS data lines and clock inputs to avoid cross-talk during register writes.
Informations de conformité
RoHS/lead-free compliance per the #PBF datasheet suffix on distributor listings. Halogen-free status not stated in the provided data (marked unknown). Not AEC-Q100 qualified; this part targets commercial/industrial base-station, radar and instrumentation markets, not automotive.
