LTC2164CUK - 16-Bit 105Msps Low Power ADC | Analog Devices
料号： LTC2164CUK ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.65 | $346.50 |
| 100 | $30.8 | $3,080.00 |
| 500 | $27.5 | $13,750.00 |
| 1,000 | $24.75 | $24,750.00 |
LTC2164CUK 概述
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous analog waveform and produces a discrete multi-bit digital representation. Pipelined ADCs, the family to which the LTC2164CUK belongs, use a multi-stage sub-ADC/MDAC/flash architecture to achieve 14-16 bit resolution at tens to hundreds of mega-samples per second while keeping per-stage hardware costs manageable. Within the broader taxonomy, the LTC2164CUK sits at: ADC -> pipelined ADC -> data converter -> mixed-signal IC -> semiconductor. Pipelined parts are the dominant choice for communications infrastructure, defense electronics and high-end instrumentation where 16-bit dynamic range at IF frequencies is mandatory.
Key features of the LTC2164CUK include a single 1.8 V analog supply (with separate digital output supply rail for flexible interfacing), selectable CMOS, DDR CMOS or LVDS output modes, a serial SPI port for mode configuration, integrated shutdown and nap power-save modes, and AC performance that targets demanding communications front-end applications. The part accepts single-ended or differential analog inputs and provides an integrated input common-mode bias network, reducing the external component count on the front-end anti-alias filter.
The LTC2164CUK uses a switched-capacitor pipelined core calibrated at the Analog Devices factory. Internal error-correction logic and digital post-processing yield consistent 76.8 dB SNR and 90 dB SFDR across the IF band of interest. Designers typically pair it with a low-jitter ADC clock buffer (e.g. AD9516 or HMC7044) and a bandpass anti-alias filter. Differential transformer coupling (e.g. ADT1-1WT or Mini-Circuits ADT2-1T) is the standard input configuration to preserve second-order distortion performance.
Typical applications for the LTC2164CUK include wireless base-station receivers, LTE/UMTS and CDMA digitizing IF stages, radar and electronic-warfare intermediate-frequency sampling, broadband software-defined radio (SDR), cable-headend downstream digitizers, and high-end medical imaging front ends. The combination of 16-bit resolution and 105 Msps throughput also makes it useful in scientific test instrumentation and ultrasonic nondestructive testing.
A key design consideration with the LTC2164CUK is clock jitter. Although the part's 0.07 psRMS aperture jitter is exceptionally low, total system SNR is dominated by the analog input frequency multiplied by external clock jitter. Designers should budget at least 0.5 ps of clock-source jitter for IF inputs above 70 MHz, and use a dedicated clock distribution buffer or PLL to keep the sampling edge clean. The exposed pad of the QFN-48 must be soldered to a continuous low-impedance ground plane for thermal and electrical performance.
This page synthesizes distributor stock and pricing, drop-in pin-compatible alternatives, and practical PCB layout notes that supplement the official Analog Devices datasheet family.
直接替换替代料： LTC2164CUK ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2164CUK （相同外形与封装尺寸） ——差异在于 Architecture, Package, Resolution, Analog Supply Voltage, Aperture Jitter.
快速对比工具——选择替代料号进行并排对比：
LTC2165CUK
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$58.53 / 个
查看数据手册 →LTC2163CUK
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
LTC2260IUK
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
LTC2259IUK
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
LTC2151CUJ-14
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$29.1 / 个
查看数据手册 →LTC2164CUK 最大额定值与电气特性
| 分辨率 | 16 bits |
| Sample Rate (max) | 105 Msps |
| Number of Channels | 1 |
| Converter Type | Pipelined ADC |
| Input Type | Single-ended or differential analog |
| Analog Supply Voltage | 1.8 V (typ) |
| Digital Output Supply | Selectable, compatible with CMOS/LVDS interface |
| Output Interface | CMOS, DDR CMOS, or LVDS (selectable) |
| SNR | 76.8 dB |
| SFDR | 90 dB |
| Aperture Jitter | 0.07 psRMS |
| Configuration Interface | Serial SPI port |
| Power-Save Modes | Shutdown and nap modes |
| 封装 | 48-pin QFN (7x7) with exposed pad |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant (Pb-free #PBF suffix) |
| Temperature Grade | Commercial |
| Architecture | Switched-capacitor pipelined, factory-calibrated |
LTC2164CUK 引脚配置
| 引脚 1 | GND — Ground |
| 引脚 2 | AINA+ — Differential analog input, positive |
| 引脚 3 | AINA- — Differential analog input, negative |
| 引脚 4 | VCM — Common-mode voltage for analog input |
| 引脚 5 | REFT — Internal reference top, decouple to ground |
| 引脚 6 | REFB — Internal reference bottom, decouple to ground |
| 引脚 7 | VREF — Internal reference voltage, decouple to ground |
| 引脚 8 | SENSE — Reference mode sense input |
| 引脚 9 | OGND — Output buffer ground |
| 引脚 10 | OVDD — Output supply voltage |
| 引脚 11 | D0+ — Digital output bit 0, positive |
| 引脚 12 | D0- — Digital output bit 0, negative (LVDS pair) |
| 引脚 13 | D1+ — Digital output bit 1, positive |
| 引脚 14 | D1- — Digital output bit 1, negative (LVDS pair) |
| 引脚 15 | D2+ — Digital output bit 2, positive |
| 引脚 16 | D2- — Digital output bit 2, negative (LVDS pair) |
| 引脚 17 | D3+ — Digital output bit 3, positive |
| 引脚 18 | D3- — Digital output bit 3, negative (LVDS pair) |
| 引脚 19 | D4+ — Digital output bit 4, positive |
| 引脚 20 | D4- — Digital output bit 4, negative (LVDS pair) |
| 引脚 21 | D5+ — Digital output bit 5, positive |
| 引脚 22 | D5- — Digital output bit 5, negative (LVDS pair) |
| 引脚 23 | D6+ — Digital output bit 6, positive |
| 引脚 24 | D6- — Digital output bit 6, negative (LVDS pair) |
| 引脚 25 | D7+ — Digital output bit 7, positive |
| 引脚 26 | D7- — Digital output bit 7, negative (LVDS pair) |
| 引脚 27 | D8+ — Digital output bit 8, positive |
| 引脚 28 | D8- — Digital output bit 8, negative (LVDS pair) |
| 引脚 29 | D9+ — Digital output bit 9, positive |
| 引脚 30 | D9- — Digital output bit 9, negative (LVDS pair) |
| 引脚 31 | D10+ — Digital output bit 10, positive |
| 引脚 32 | D10- — Digital output bit 10, negative (LVDS pair) |
| 引脚 33 | D11+ — Digital output bit 11, positive |
| 引脚 34 | D11- — Digital output bit 11, negative (LVDS pair) |
| 引脚 35 | D12+ — Digital output bit 12, positive |
| 引脚 36 | D12- — Digital output bit 12, negative (LVDS pair) |
| 引脚 37 | D13+ — Digital output bit 13, positive |
| 引脚 38 | D13- — Digital output bit 13, negative (LVDS pair) |
| 引脚 39 | D14+ — Digital output bit 14, positive |
| 引脚 40 | D14- — Digital output bit 14, negative (LVDS pair) |
| 引脚 41 | D15+ — Digital output bit 15, positive (MSB) |
| 引脚 42 | D15- — Digital output bit 15, negative (LVDS pair) |
| 引脚 43 | ENC+ — Encode (sample clock) input, positive |
| 引脚 44 | ENC- — Encode (sample clock) input, negative |
| 引脚 45 | VDD — Analog supply voltage 1.8 V |
| 引脚 46 | CS — SPI chip select (active low) |
| 引脚 47 | SDI — SPI serial data input |
| 引脚 48 | SCK — SPI serial clock |
| 引脚 EP | Exposed Pad (GND) — Thermal/ground pad, solder to PCB ground plane |
典型应用
LTC2164CUK 适用于 6 应用s: Wireless Base Station Receiver IF Sampling, Radar and Electronic Warfare IF Digitizer, Broadband Software Defined Radio (SDR), Cable Headend Downstream Digitizer, High-End Medical Imaging Front End, Scientific Test and Measurement Instrumentation.
Wireless Base Station Receiver IF Sampling
The LTC2164CUK's 16-bit resolution, 105 Msps throughput and 0.07 psRMS aperture jitter make it ideally suited for digitizing intermediate-frequency signals inside LTE, UMTS and CDMA base-station receivers. The part supports undersampling of IF frequencies up to several hundred MHz with 76.8 dB SNR and 90 dB SFDR, ensuring that small-signal information above the noise floor is preserved for downstream channelization. A typical signal chain places the LTC2164CUK after a 2nd-IF bandpass filter and a 1:1 RF transformer for differential drive, clocked from a low-jitter source such as AD9516. Unlike an FPGA-based decimator at the same node, this ADC converts directly to digital at the IF, simplifying timing closure and eliminating analog BB stages.
推荐
Radar and Electronic Warfare IF Digitizer
The combination of 76.8 dB SNR, 0.07 psRMS aperture jitter and 90 dB SFDR allows the LTC2164CUK to undersample intermediate-frequency radar returns directly, preserving target amplitude information across a wide instantaneous bandwidth. Pin compatibility with the 48-pin 7x7 QFN package family lets system designers reuse a single ADC layout across multiple speed grades (LTC2163/LTC2164/LTC2165) for subsystem scalability. Differential transformer drive at the analog input preserves second-harmonic distortion performance below -90 dBc. Compared with lower-jitter discrete track-and-hold plus flash solutions, the integrated ADC simplifies thermal management and reduces parts count on the RF/IF board, which is especially valuable in size-constrained EW payload applications.
推荐
Broadband Software Defined Radio (SDR)
In broadband software-defined radio platforms the LTC2164CUK digitizes wideband RF/IF signals directly to baseband, offloading filtering and demodulation to an FPGA or DSP. Its selectable CMOS, DDR CMOS or LVDS digital output modes support direct connection to modern FPGAs with 1.8 V LVDS I/O, removing the need for external level translators. The integrated SPI configuration port allows real-time trade-off between output mode, gain and shutdown settings under software control. The 120 mW typical power consumption at 105 Msps keeps thermal rise modest in outdoor or backpack SDR enclosures. This flexibility makes the LTC2164CUK a foundation block in tactical, public-safety and engineering SDR products.
推荐
Cable Headend Downstream Digitizer
Cable-TV headend receivers require 16-bit dynamic range to capture hundreds of QAM channels to within 0.5 dB amplitude accuracy, and the LTC2164CUK's 76.8 dB SNR and 90 dB SFDR meet this goal at IF sample rates up to 105 Msps. Its integrated input common-mode bias network reduces external component count on the front-end diplexer/AGC network, while the CMOS/LVDS outputs let the headend modulator cluster use 1.8 V FPGA logic. Compared with dual-channel ADCs the LTC2164CUK's single-channel architecture simplifies thermal layout on densely populated line-card designs. The exposed-pad QFN package provides a low-thermal-resistance path for headend chassis with limited airflow.
推荐
High-End Medical Imaging Front End
In ultrasound, CT and MRI receiver chains, the LTC2164CUK's 16-bit resolution and 105 Msps throughput allow direct digitization of beamformed RF signals at the probe handle or front-end card. The 76.8 dB SNR provides the dynamic range required to resolve small tissue echoes next to strong specular reflections, while the 0.07 psRMS aperture jitter supports IF undersampling for tighter sub-array footprints. Pin compatibility across the LTC2163/2164/2165 family allows a single PCB to scale with channel count or sample-rate requirements. The configurable SPI port lets field engineers adjust power-versus-bandwidth modes during calibration without altering the BOM.
推荐
Scientific Test and Measurement Instrumentation
Wide-bandwidth oscilloscopes, spectrum analyzers and arbitrary waveform digitizers all rely on 16-bit data converters to push dynamic range past legacy 12-14 bit front ends. The LTC2164CUK's pipelined architecture and 0.07 psRMS aperture jitter allow direct IF sampling of signals up to several hundred MHz, replacing traditional analog-downconvert sections with a more compact digital-IF stage. Pin compatibility across the 7x7 QFN-family lets designers reuse the same analog front-end PCB for multiple speed grades (LTC2163/2164/2165). The exposed-pad package keeps thermal rise modest at full 105 Msps operation, an important consideration in densely populated bench-instrument chassis with constrained airflow.
推荐
推荐产品汇总
工程参考数据： LTC2164CUK ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2165CUK | LTC2163CUK | LTC2260IUK | LTC2259IUK | LTC2151CUJ-14 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 48-pin QFN (7x7) with exposed pad | 48-pin QFN (7x7) - same | 48-pin QFN (7x7) - same | 48-pin QFN (7x7) - same | 48-pin QFN (7x7) - same | 48-pin QFN (7x7) - same |
| Resolution | 16 bit | 16 bit | 16 bit | 14 bit | 14 bit | 14 bit |
| Maximum Sample Rate | 105 Msps | 125 Msps | 80 Msps | 125 Msps | 80 Msps | 40 Msps |
| Output Interface | CMOS, DDR CMOS, LVDS | CMOS, DDR CMOS, LVDS | CMOS, DDR CMOS, LVDS | CMOS, DDR CMOS, LVDS | CMOS, DDR CMOS, LVDS | CMOS, DDR CMOS, LVDS |
关键差异点
- Mid-speed 105 Msps throughput places it between 80 Msps LTC2163 and 125 Msps LTC2165 in the same family, allowing designers to tune speed/cost without PCB changes （对比 LTC2163CUK)
- 76.8 dB SNR and 90 dB SFDR are identical to the LTC2165CUK and LTC2163CUK, so 105 Msps is the sweet spot for price-per-Msps in this family （对比 LTC2260IUK)
- 0.07 psRMS aperture jitter supports undersampling of IF frequencies above 200 MHz with negligible SNR penalty （对比 LTC2163CUK)
设计说明
Estimated SNR loss due to external clock jitter scales as 20*log10(2*pi*f_analog*jitter_ext). For a 95 MHz IF input and an external clock jitter of 1 psRMS the SNR penalty is approximately 54.6 dB, well above the ADC's intrinsic 76.8 dB SNR. Always budget a clock source and clock buffer with sub-0.3 psRMS jitter when the analog input frequency exceeds 70 MHz, otherwise the system's effective SNR will be dominated by the clock rather than the ADC.
Estimated: route the differential AINA+/AINA- and ENC+/ENC- inputs with 100 ohm differential impedance and length-matched traces within 2 mm of each other. Place a 0.1 uF X7R ceramic bypass capacitor within 1-2 mm of each VDD and OVdd pin, and a bulk 4.7 uF tantalum or polymer capacitor within 5 mm of the analog supply rail. The QFN exposed pad must be soldered directly to a continuous, low-inductance ground plane for thermal dissipation and electrical ground integrity.
Estimated: isolate the analog (AIN, REFT, REFB, VREF, VCM) and digital (Dxx, OVDD, OGND) grounds and merge them at a single point, typically directly under the part's exposed pad. Separating the analog and digital grounds prevents digital switching noise from coupling into the analog input, which would otherwise degrade SFDR by 10-15 dB. Additionally, keep the SPI configuration traces (CS, SDI, SCK) away from the parallel LVDS data lines and clock inputs to avoid cross-talk during register writes.
合规信息
RoHS/lead-free compliance per the #PBF datasheet suffix on distributor listings. Halogen-free status not stated in the provided data (marked unknown). Not AEC-Q100 qualified; this part targets commercial/industrial base-station, radar and instrumentation markets, not automotive.
