SN74LS138 - 3-to-8 Decoder/Demultiplexer LS-TTL | TI
Référence : SN74LS138 ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $0.65 | $0,65 |
| 10 | $0.55 | $5,50 |
| 100 | $0.42 | $42,00 |
| 500 | $0.35 | $175,00 |
| 1 000 | $0.28 | $280,00 |
SN74LS138 Présentation
A decoder is a combinational logic circuit that converts binary information from n input lines to a maximum of 2^n unique output lines. The 3-to-8 decoder is a fundamental building block in digital systems, used to select one of eight devices based on a 3-bit address. As an MSI device, it sits between SSI gates and LSI circuits in the digital logic hierarchy, and decoders are essential in memory address decoding where they enable specific memory chips.
Key features include a typical propagation delay of 20 ns, low LS-TTL power dissipation (about 32 mW typical), and active-low outputs that sink up to 8 mA. The three enable inputs allow cascading multiple decoders into larger arrays (e.g., 4-to-16) and gating the device with control signals. Schottky-clamped TTL technology delivers high speed with good noise immunity and full TTL compatibility with 74LS, 74ALS, and 74AS families.
The device is offered in 16-pin PDIP (N), SOIC (D), and SOP (NS) packages; the SN74LS138N in 16-PDIP is popular for through-hole and breadboard prototyping. According to the TI datasheet, the SN74LS138 is characterized from 0C to 70C for commercial operation.
Typical applications include memory chip-select decoding in microprocessor systems, peripheral address decoding, and demultiplexing a single data line to one of eight outputs.
Design tip: enable the device by driving G1 high and G2A/G2B low; tie unused inputs to valid logic levels to avoid floating nodes, and exploit the active-low outputs to drive active-low chip-select pins directly.
Alternatives de remplacement direct pour SN74LS138 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec SN74LS138 (même facteur de forme et même empreinte) — différant par Enable Inputs, Logic Family, Mounting Type, Package, Select Inputs.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
SN74S138A
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
SN74LS138N
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
SN74HC138N
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
CD74HC138
✅ Remplacement direct✓ En stock
$0.18 / unité
Voir la fiche technique →74HCT138
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
SN74LS138 Valeurs maximales et caractéristiques électriques
| Fonction | 3-line to 8-line Decoder/Demultiplexer |
| Logic Family | 74LS (Schottky-clamped TTL) |
| Tension d'alimentation | 5 V (TTL levels) |
| Propagation Delay | 20 ns (typical) |
| Outputs | 8 active-low (Y0-Y7) |
| Select Inputs | 3 (A, B, C) |
| Enable Inputs | 3 (G1 active-high, G2A/G2B active-low) |
| Output Sink Current | 8 mA |
| Power Dissipation | 32 mW (typical) |
| Température de fonctionnement | 0C to +70C |
| Boîtier | 16-PDIP (N) |
| Other Packages | SOIC (D), SOP (NS) |
| Type de montage | Through Hole (PDIP variant) |
| Technology | Bipolar TTL MSI |
| Applications | High-performance memory decoding, data routing |
Configuration des broches de SN74LS138
| Broche 1 | A — Select input A (LSB) |
| Broche 2 | B — Select input B |
| Broche 3 | C — Select input C (MSB) |
| Broche 4 | G2A — Enable input, active-low |
| Broche 5 | G2B — Enable input, active-low |
| Broche 6 | G1 — Enable input, active-high |
| Broche 7 | Y7 — Output 7, active-low |
| Broche 8 | GND — Ground |
| Broche 9 | Y6 — Output 6, active-low |
| Broche 10 | Y5 — Output 5, active-low |
| Broche 11 | Y4 — Output 4, active-low |
| Broche 12 | Y3 — Output 3, active-low |
| Broche 13 | Y2 — Output 2, active-low |
| Broche 14 | Y1 — Output 1, active-low |
| Broche 15 | Y0 — Output 0, active-low |
| Broche 16 | VCC — Supply voltage, 5 V |
Applications typiques
SN74LS138 convient pour 6 applications: Memory Chip-Select Decoding, Peripheral Address Decoding, Data Demultiplexing, Cascaded 4-to-16 Decoding, LED and Indicator Sequencing, Breadboard Prototyping and Education.
Memory Chip-Select Decoding
The primary application of the SN74LS138 per its TI datasheet is high-speed bipolar memory chip-select address decoding. The three select inputs (A, B, C) decode a 3-bit address into one of eight active-low outputs that directly drive memory device CS/ pins, with only 20 ns typical propagation delay preserving microprocessor memory-cycle timing budgets. Placed on the upper address bus bits, it activates exactly one memory chip per access; the enables (G1, G2A, G2B) can gate decoding with bus control signals to prevent spurious chip selects during address transitions.
Recommandé
Peripheral Address Decoding
In embedded systems with multiple I/O peripherals sharing a bus, the SN74LS138 decodes address bits to generate individual peripheral select strobes. Its 8 mA output sink capability directly drives active-low chip-enable inputs of UARTs, timers, and parallel ports without external buffers, and the 20 ns delay adds negligible latency to I/O cycles. The three enable inputs allow bank-switching: one enable can be tied to a memory-mapped I/O region signal, restricting peripheral selection to the correct address space and eliminating bus conflicts.
Recommandé
Data Demultiplexing
With data applied to one enable input (e.g., G1) and the address on A/B/C, the SN74LS138 routes a single data stream to one of eight outputs, functioning as a 1-to-8 demultiplexer. According to the TI datasheet, the outputs are active-low, so an enabled output inverts the data - a simple inverter recovers polarity, or system logic can account for it. This suits serial-to-parallel fan-out of control signals such as LED column drives, relay select lines, or test-equipment channel activation with deterministic 20 ns routing delay.
Recommandé
Cascaded 4-to-16 Decoding
Two SN74LS138 devices cascade into a 4-to-16 decoder using the enable architecture: the MSB drives G1 of the upper decoder and G2A of the lower decoder, G2B is grounded on both, and the lower three address bits are shared. This configuration yields sixteen active-low selects with one added stage of enable delay only. The scheme extends to 5-to-32 with four devices and a secondary decoder, a standard technique in larger memory arrays and legacy backplane designs where 74LS timing and drive characteristics must remain uniform.
Recommandé
LED and Indicator Sequencing
The SN74LS138 drives LED columns, indicator banks, or discrete status displays by decoding a counter or microcontroller port into one-of-eight active-low select lines. Each output sinks up to 8 mA, sufficient to sink current directly through an LED with a series resistor in common-anode configurations. Scanning eight columns with a 3-bit counter running at moderate frequency yields multiplexed displays with a 1:8 duty cycle; the fast 20 ns decode transition minimizes ghosting between columns, and the enable inputs blank the entire bank between frames.
Recommandé
Breadboard Prototyping and Education
The 16-PDIP SN74LS138N package is a staple of through-hole breadboard prototyping and digital logic education, illustrating combinational decoding, enable logic, and demultiplexing concepts with a classic 74LS MSI device. Its TTL 5V supply, standard 0.1-inch pin pitch, and widely documented function table (per the TI datasheet) make it beginner-friendly, while active-low outputs teach logic polarity conventions. Students commonly pair it with counter ICs for sequencers and with memory chips for address-decoding labs, and it is interchangeable with HC-family equivalents for lower-power experiments.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour SN74LS138 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | SN74S138A | SN74LS138N (onsemi) | SN74HC138N | CD74HC138 | 74HCT138 |
|---|---|---|---|---|---|---|
| Package | 16-PDIP (N) | 16-PDIP (N) - same | 16-PDIP (N) - same | 16-PDIP (N) - same | 16-PDIP (N) - same | 16-PDIP (N) - same |
| Brand | Texas Instruments | Texas Instruments | onsemi | Texas Instruments | Texas Instruments | NXP Semiconductors |
| Logic Family | 74LS (Schottky TTL) | 74S (standard Schottky TTL) | 74LS (Schottky TTL) | 74HC (CMOS) | 74HC (CMOS) | 74HCT (CMOS, TTL thresholds) |
| Supply Voltage | 5 V (TTL) | 5 V (TTL) | 5 V (TTL) | 2 V to 6 V | 2 V to 6 V | 4.5 V to 5.5 V |
| Power Dissipation | 32 mW (typ) | Higher than LS | 32 mW (typ) | Much lower (CMOS) | Much lower (CMOS) | Much lower (CMOS) |
| Operating Temperature | 0C to +70C | 0C to +70C | 0C to +70C | -40C to +85C | -55C to +125C (ceramic variants) | -40C to +125C |
| Output Type | 8 active-low outputs | 8 active-low outputs - same | 8 active-low outputs - same | 8 active-low outputs - same | 8 active-low outputs - same | 8 active-low outputs - same |
Principaux différenciateurs
- True LS-TTL second-source ecosystem (vs SN74HC138N)
- Three-input enable for cascading and gating (vs Simple decoder gates)
- Lower power than SN74S138A (vs SN74S138A)
Notes de conception
Enable the device by driving G1 high and both G2A and G2B low; any unmet enable condition forces all outputs high (inactive). Tie all three enable pins to valid static levels if cascading is not used - floating enables cause spurious output glitches. Unused select inputs must also be tied to VCC or GND, never left floating, as TTL inputs that float can pick up noise and randomly change the decoded output.
Decouple VCC (pin 16) to GND with a 0.1 uF ceramic capacitor placed within a few millimeters of the pin. LS-TTL devices draw current spikes during output switching; without local decoupling, ground bounce can falsely trigger adjacent logic. At 32 mW typical dissipation no heatsinking is required, but total supply current grows with output loading - account for up to 8 mA sunk per active output in your 5V rail budget.
The 20 ns typical propagation delay is a typ spec; design timing margins using the datasheet maximum values at your temperature and load conditions. When driving long lines or memory chip-selects, note that active-low outputs sinking 8 mA have asymmetric rise (passive pull-up, ~few hundred ohms) and fall times - critical edges are falling edges. For mixed-family designs, remember HC CMOS inputs may not meet TTL VOH thresholds when driven directly from LS outputs; prefer 74HCT138 in such upgrades.
Informations de conformité
Compliance data not present in provided verified web data; check TI product page for current RoHS/REACH status. Note that original LS-TTL parts may be non-RoHS; RoHS-compliant suffix variants (e.g., -G4 or -E4) may exist.
