CD74HC138 - 3-to-8 Line Decoder/Demux | Texas Instruments
MPN: CD74HC138 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0.45 | $0.45 |
| 10 | $0.38 | $3.80 |
| 100 | $0.28 | $28.00 |
| 500 | $0.22 | $110.00 |
| 1,000 | $0.18 | $180.00 |
Drop-in alternatives for CD74HC138 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
SN74HC138N
β Drop-Inπ Reference alternative (not in catalog)
CD74HCT138E
β Drop-Inπ Reference alternative (not in catalog)
CD74HC238E
β‘ Same Packageπ Reference alternative (not in catalog)
MC74HC138ANG
β Drop-Inπ Reference alternative (not in catalog)
74HC138N
β Drop-Inπ Reference alternative (not in catalog)
CD74HC138 Maximum Ratings & Electrical Characteristics
| Function | 3-to-8 Line Decoder/Demultiplexer, Inverting Outputs |
| Logic Family | High Speed CMOS (HC) |
| Supply Voltage Range | 2 V to 6 V |
| Number of Select Inputs | 3 (A0, A1, A2) |
| Number of Outputs | 8 (Y0 to Y7, active low) |
| Enable Inputs | 3 (E1, E2 active low; E3 active high) |
| Output Type | Inverting (active low) |
| Technology | Silicon-gate CMOS |
| Operating Temperature | -55C to +125C |
| Package | 16-pin (PDIP, SOIC, variants) |
| Mounting Type | Through Hole / Surface Mount (per package variant) |
| Typical Application | Memory address decoding, data routing |
| Propagation Delay | [DATA_NEEDED: propagation delay at specified Vcc] |
| Quiescent Current | [DATA_NEEDED: ICC value] |
| RoHS Status | [DATA_NEEDED: RoHS status] |
CD74HC138 Pin Configuration
| Pin 1 | A0 β Select input 0 (LSB) |
| Pin 2 | A1 β Select input 1 |
| Pin 3 | A2 β Select input 2 (MSB) |
| Pin 4 | E1 (E-) β Enable input, active low |
| Pin 5 | E2 (E-) β Enable input, active low |
| Pin 6 | E3 (E+) β Enable input, active high |
| Pin 7 | Y7 β Output 7, active low |
| Pin 8 | GND β Ground |
| Pin 9 | Y6 β Output 6, active low |
| Pin 10 | Y5 β Output 5, active low |
| Pin 11 | Y4 β Output 4, active low |
| Pin 12 | Y3 β Output 3, active low |
| Pin 13 | Y2 β Output 2, active low |
| Pin 14 | Y1 β Output 1, active low |
| Pin 15 | Y0 β Output 0, active low |
| Pin 16 | VCC β Supply voltage (2V to 6V) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
CD74HC138 is suitable for 6 applications: Memory Address Decoding, Microprocessor I/O Port Expansion, Data Routing / Demultiplexing, Industrial Control and Relay Select Logic, Test and Measurement Instrumentation, LED and Display Segment Selection.
Memory Address Decoding
The CD74HC138 excels at memory address decoding, its primary intended application per TI datasheet SCHS147J. The three select inputs (A0-A2) decode high address bits into eight active-low outputs that directly drive SRAM, EPROM, or Flash chip-select (CS/CE) pins without external inverters, reducing propagation delay in the memory access path. The three enable inputs (E1, E2 active low; E3 active high) allow combine/enable gating with bus control signals such as MREQ or READ, and support cascading two devices into a 4-to-16 decoder for larger memory maps. Low CMOS quiescent power keeps decoder overhead minimal in battery or embedded systems.
Recommended
Microprocessor I/O Port Expansion
In microprocessor systems, the CD74HC138 expands a few address lines into eight chip-select signals for peripherals such as UARTs, timers, and port expanders. The active-low outputs match the active-low chip-enable convention of most peripheral ICs, eliminating glue logic. Enables can be tied to a bus read/write strobe so the decoder only asserts a select during valid bus cycles, preventing spurious peripheral activation. With LSTTL-comparable speed and CMOS low power, the HC138 keeps the expansion logic simple and power-efficient while providing deterministic one-hot selection across the I/O map.
Recommended
Data Routing / Demultiplexing
Used as a 1-of-8 demultiplexer, the CD74HC138 routes a serial data stream applied at an active-low enable to one of eight outputs selected by A0-A2. Because the enable-to-output path is a fast, direct gate path, the demultiplexing delay is short and well matched across all eight channels. The inverting outputs reproduce the (inverted) data at the selected channel, which suits driving active-low control buses or LED indications with pull-ups. Designers should account for the output inversion in firmware or add a subsequent inverter if non-inverted data routing is required.
Recommended
Industrial Control and Relay Select Logic
In industrial automation panels, the CD74HC138 decodes binary control words from PLCs or microcontrollers into eight discrete channel-select signals for relay drivers, sensors, or actuator mux banks. The 2V to 6V HC supply range and -55C to +125C rated operation give margin in electrically noisy, wide-temperature cabinets. Active-low outputs can directly drive PNP transistor or P-channel MOSFET driver stages. Keep decoder inputs protected with series resistors and clamp diodes near long field wiring, and debounce or latch select lines to avoid chatter on relay drivers.
Recommended
Test and Measurement Instrumentation
Bench instruments and automated test equipment use the CD74HC138 to select one of eight signal paths, sensor banks, or calibration relays from a microcontroller's binary output. HC-family speed (LSTTL-comparable) keeps channel-switching overhead low during scans, while CMOS inputs draw negligible loading on control lines. The three enables allow a single decoder bank to be disabled (all outputs high) between measurement cycles, reducing cross-channel leakage and glitches. For sensitive analog front ends, place the decoder's supply away from analog rails and route active-low select lines with adequate spacing to guard analog signals.
Recommended
LED and Display Segment Selection
The CD74HC138 provides one-of-eight selection for LED indicators, seven-segment digit drives in multiplexed displays, and status panels. Only one output is asserted at a time, so multiplexed display scanning is straightforward: increment A0-A2 each scan period and drive segment data in sync. With pull-up resistors, active-low outputs sink current through the selected LED path; the HC output can source/sink modest LSTTL-level current - verify drive current limits from the datasheet and add transistor or driver buffers for high-current LED strings. Cascading two devices gives 16-way digit selection for larger displays.
Recommended
Recommended Products Summary
Engineering reference data for CD74HC138 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SN74HC138N | CD74HCT138E | MC74HC138ANG | 74HC138N |
|---|---|---|---|---|---|
| Package | 16-pin (PDIP/SOIC variants) | PDIP-16 - same pinout | PDIP-16 - same pinout | PDIP-16 - same pinout | PDIP-16 - same pinout |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | onsemi | Nexperia |
| Function | 3-to-8 decoder/demux, inverting | 3-to-8 decoder/demux, inverting | 3-to-8 decoder/demux, inverting | 3-to-8 decoder/demux, inverting | 3-to-8 decoder/demux, inverting |
| Output Polarity | Active low | Active low | Active low | Active low | Active low |
| Supply Voltage Range | 2 V to 6 V (HC) | 2 V to 6 V | 4.5 V to 5.5 V (HCT) | 2 V to 6 V | 2 V to 6 V |
| Input Thresholds | CMOS levels | CMOS levels | TTL-compatible levels | CMOS levels | CMOS levels |
| Enable Inputs | 3 (2 active low, 1 active high) | 3 (same structure) | 3 (same structure) | 3 (same structure) | 3 (same structure) |
| Approx. Price (1 pc, as of 2026-08-29) | $0.45 | $0.45 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- CMOS-level HC inputs at low power (vs CD74HCT138E)
- Inverting outputs for active-low chip selects (vs CD74HC238E)
- Active TI product line with full datasheet support (vs MC74HC138ANG)
Design Notes
Tie all three enable inputs to defined levels - a floating enable leaves outputs undefined and can cause bus contention. For standard decoding, ground E1 and E2 (active low) and tie E3 high; reserve enables for cascading or strobe gating. Also remember all outputs are inverting: a selected output goes LOW, so active-high loads need a subsequent inverter or use the CD74HC238 non-inverting version instead.
Place 0.1uF ceramic decoupling capacitor within a few millimeters of the VCC pin on every HC138 in the system; HC devices switch fast enough to inject supply transients into neighboring analog circuitry. Keep A0-A2 select lines equal length where skew matters (memory decoding across simultaneous address changes) and route enable strobes away from clock lines to prevent decode glitches during transitions.
When cascading two HC138s for 4-to-16 decoding, decode glitches can appear on outputs while select lines settle if the MSB path is much slower than A0-A2. If downstream loads are sensitive (e.g., driving RAM CS during write), register the select inputs or strobe the enables after address settling per TI datasheet SCHS147J timing guidance.
Compliance Information
Compliance data not present in provided web data; verify on TI product page for the specific package suffix. Note: the CD74HC138-Q1 variant exists for automotive applications.
