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DP83826IRHBT - 10/100 Industrial Ethernet PHY | Texas Instruments
The Texas Instruments DP83826IRHBT is a low-latency 10/100-Mbps Ethernet physical-layer transceiver with MII and RMII interfaces, IEEE 802.3 support, and an industrial operating-temperature range in a 32-pin VQFN RHB package. It supports 10BASE-Te and 100BASE-TX Ethernet protocols for industrial communication systems. An Ethernet PHY is the physical-layer component that translates digital MAC traffic into signals suitable for twisted-pair cabling and recovers those signals at the receiving endpoint. In the networking hierarchy, the DP83826IRHBT is a single-port Ethernet transceiver, placing it between a network media-access controller and the 100-MHz or 10-Mbps copper Ethernet medium. Its MII interface supports integration with conventional Ethernet controllers, while RMII provides a lower-pin-count alternative for suitable embedded processors. Key characteristics include support for both 10BASE-Te and 100BASE-TX, a maximum link rate of 100 Mbps, deterministic low latency, low-power operation, and MII plus RMII interfaces. The industrial-temperature designation makes the device applicable to factory automation, industrial controls, embedded communications equipment, and other systems operating beyond typical commercial environments. The exposed-pad VQFN package also supports compact PCB layouts and improved thermal performance when the pad is connected to an appropriate ground plane. The device is positioned for deterministic industrial Ethernet networks, where repeatable signal timing and predictable link behavior are important. The MII interface provides a parallel data path commonly used by Ethernet controllers, whereas RMII reduces the number of required interface signals when the host controller supports it. Auto-negotiation between 10-Mbps and 100-Mbps operation is part of the IEEE 802.3 feature set identified by the verified distributor data. Typical uses include industrial Ethernet switches, programmable-logic-controller communication ports, industrial gateways, embedded control systems, and test equipment requiring a reliable copper-network interface. In these systems, the DP83826IRHBT can sit between an Ethernet MAC or processor and an isolated or non-isolated transformer-coupled network port, depending on the reference design and regulatory requirements. Designers should confirm the exact pin functions, recommended magnetics, termination network, external clock requirements, exposed-pad layout, and bypass-capacitor values against the manufacturer data sheet before release. PCB signal-integrity and thermal reviews are particularly important because Ethernet PHY performance depends on controlled return paths and a low-impedance ground reference around the device. This product page consolidates verified manufacturer and distributor information, drop-in alternatives supported by the supplied cross-reference results, comparison parameters, and practical design considerations for engineers evaluating the DP83826IRHBT.
DP83840AVCE - 10/100 Ethernet PHY | Texas Instruments
Texas Instruments DP83840AVCE is a single-channel Ethernet physical-layer controller for 10 Mb/s and 100 Mb/s copper links, supplied in a 100-pin PQFP package measuring 14 mm by 20 mm. It supports 10BASE-T and 100BASE-TX operation from a 4.75 V to 5.25 V supply and consumes approximately 335 mA. An Ethernet physical layer, or Ethernet PHY, is the interface between a digital network controller and physical copper or fiber media. The DP83840AVCE implements the analog and digital signaling needed to communicate over twisted-pair cabling, while an upper-layer MAC handles packet framing, addressing, and higher-level protocols. Its 10/100 capability allows equipment to support both legacy 10 Mb/s networks and Fast Ethernet links through one physical interface. Key verified characteristics include support for 10/100BASE-T/TX, a 4.75 V to 5.25 V operating supply range, and approximately 335 mA supply current. The 100-pin PQFP package provides the connections required for integrated PHY functions, clocking, power, status, and media-interface signaling. Distributor listings identify the component as a 100-PQFP Ethernet physical-layer controller, and the package is supplied in tray packaging. The device is designed for industrial and embedded systems that require an IEEE 802.3af-compatible Ethernet interface. Relevant implementation considerations include proper magnetics coupling to an RJ45 connector, controlled clock and power distribution, compliant board layout, and isolation from high-energy network transients. Because the DP83840AVCE is listed as obsolete by one distributor, engineers should also confirm the availability of authorized inventory before beginning a new production design. Typical uses include industrial Ethernet equipment, embedded controllers, network interface appliances, test equipment, and communications infrastructure. The 10BASE-T capability can provide compatibility with installed 10 Mb/s infrastructure, while 100BASE-TX supports higher-throughput Fast Ethernet applications. System designers must still evaluate total board area, thermal behavior, component availability, and medium requirements around the obsolete-product status. The main engineering trade-off is legacy-versus-modern network architecture. A 10/100 PHY can connect equipment to older copper networks, but it does not provide the throughput or feature set expected from current multi-gigabit Ethernet designs. For a new platform, engineers should determine whether backward compatibility justifies the 100-pin PQFP footprint and source availability. This page consolidates verified distributor specifications, lifecycle information, sourcing context, and design-focused guidance for engineers evaluating the DP83840AVCE. It also distinguishes confirmed data from specifications that require review of the complete manufacturer datasheet before PCB release.
DP83843BVJE - 10/100 Ethernet PHY | Texas Instruments
The Texas Instruments DP83843BVJE is a full-feature Ethernet physical-layer transceiver with integrated PMD sublayers, supporting 10BASE-T and 100BASE-X protocols at 10 Mb/s and 100 Mb/s. The device is supplied in an 80-pin QFP package measuring 14 mm by 14 mm. It is designed for 10/100 Mb/s Ethernet LAN implementations and provides the physical-layer interface required by a network media-access controller. An Ethernet PHY is the physical-layer device that connects a digital network controller to copper or fiber media. Within the networking hierarchy, the DP83843BVJE belongs to the Ethernet transceiver and interface-controller category, then to interface ICs and, more broadly, integrated circuits. Supporting both 10BASE-T and 100BASE-X allows one physical-layer design to address legacy 10 Mb/s copper links and 100 Mb/s Fast Ethernet links using either copper twisted-pair or optical-compatible signaling paths. The principal verified feature set includes IEEE 802.3 ENDEC operation, integrated PMD sublayers, support for 10BASE-T, support for 100BASE-X, four transmit drivers, and four receive drivers according to distributor product information. The manufacturer describes the device as a full-feature Physical Layer device intended to simplify implementation of 10/100 Mb/s Ethernet LANs. The 80-QFP package provides 80 physical terminals in a square gull-wing format. Technically, the DP83843BVJE separates Ethernet MAC-facing functions from the analog and digital signaling required by physical media. Its integrated PMD sublayers place the 10BASE-T and 100BASE-X physical coding functions inside the transceiver, reducing the amount of external media-interface circuitry required in a typical LAN design. The available verified excerpt does not provide a complete electrical timing table, register map, magnetics recommendation list, or thermal characterization, so those details must be confirmed in the complete manufacturer datasheet before schematic release. Typical uses include industrial Ethernet equipment, embedded network controllers, network interface cards, routers, switches, and other 10/100 Mb/s LAN equipment. In an industrial or embedded product, the transceiver can sit between an Ethernet MAC and the isolation or line-driver stage required by the selected 10BASE-T or 100BASE-X implementation. Board-level validation remains important because magnetics, clocking, termination, layout, and regulatory testing can determine whether a nominal PHY design functions reliably. Designers should preserve the manufacturer-recommended power, ground, and signal-integrity layout and verify every external network component against the complete datasheet. In particular, the selected Ethernet magnetics or PHY-side interface components must match the supported media mode, while differential routing and return paths require disciplined PCB implementation. Do not infer unsupported rise-time, jitter, temperature, or package thermal values from the distributor summaries. This product record combines the verified manufacturer description, distributor package information, source links, practical application context, and an explicit treatment of unavailable pin-level and electrical data. The comparison and validation notes distinguish confirmed facts from parameters that still require the full datasheet, allowing engineers to assess the DP83843BVJE efficiently without treating missing specifications as confirmed engineering data.
DP83846AVHG - 10/100 Ethernet PHY | Texas Instruments
The Texas Instruments DP83846AVHG is a single-port 10/100 Ethernet physical-layer transceiver that supports 10BASE-T and 100BASE-TX operation over Category 3 or Category 5 unshielded twisted-pair cables. It is supplied in an 80-pin LQFP package measuring 12 x 12 mm. The integrated physical-layer device provides the media-access-control physical sublayer functions required to connect an Ethernet MAC or embedded controller to a copper network. An Ethernet physical-layer transceiver, commonly called an Ethernet PHY, is the component that translates logical data into electrical signaling compatible with twisted-pair Ethernet infrastructure. Within the network-interface hierarchy, an Ethernet PHY sits between a MAC or processor and an RJ45 magnetics interface. The DP83846AVHG therefore belongs to the interface-IC and network-interface-controller ecosystem rather than acting as a standalone general-purpose processor or memory device. The verified product information identifies the DP83846AVHG as a single 10/100 Ethernet transceiver supporting both 10BASE-T and 100BASE-TX protocols. Its stated cable compatibility includes Category 3 cabling for 10 Mb/s operation and Category 5 unshielded twisted-pair cabling for 100BASE-TX operation. Distributor listings additionally identify the physical package as an 80-terminal square gull-wing LQFP in a 12 x 12 mm outline. Because the PHY combines the PMD sublayers with the Ethernet physical interface, it can simplify the hardware portion of a copper Ethernet design. The host-side interface remains coupled to the function of the associated MAC or embedded Ethernet controller, while the line-side implementation must include the specified magnetics, connector, protection, and external circuitry recommended by the manufacturer. This division keeps protocol handling separate from analog signal transmission across the cable. Typical uses include industrial control equipment, embedded Ethernet gateways, factory automation, communications infrastructure, test equipment, and compact embedded systems that need 10/100-Mb/s copper connectivity. The dual-rate support is useful where equipment must communicate over installed 10-Mb/s or 100-Mb/s networks without requiring a gigabit-only physical layer. The principal design consideration is that PCB layout, magnetic-component selection, cable-side termination, supply quality, and thermal performance can be as important as the nominal PHY capability. Designers should use the manufacturer application guidance for high-speed trace geometry, component placement, isolation, and copper-versus-fibre interfaces where applicable. External Ethernet magnetics are normally required between the PHY and the RJ45 connector unless the chosen interface architecture specifies otherwise. This product page consolidates the verified package, protocol, cable, and distributor information for DP83846AVHG and adds practical application guidance, sourcing questions, and replacement context. It distinguishes documented values from parameters that still require confirmation from the full Texas Instruments datasheet, helping engineers make a traceable initial selection before completing PCB-level validation.
DP83848IVV - 10/100 Ethernet PHY Transceiver | Texas Instruments
The Texas Instruments DP83848IVV is a single-port 10/100 Mb/s Ethernet physical layer transceiver (PHYTER) in a 48-pin LQFP (7x7 mm) package designed for reliable operation across industrial temperature ranges. The device supports IEEE 802.3u Fast Ethernet, integrating MII and RMII MAC interfaces, auto-negotiation, and on-chip echo cancellation to simplify PCB layout. An Ethernet PHY (Physical Layer Device) is a transceiver IC that sits between a MAC controller and the copper media (twisted pair), handling analog line driving/receiving, clock recovery, link monitoring, and 10BASE-T/100BASE-TX encoding/decoding. PHYTERs are a category of Ethernet PHYs that emphasize robust industrial-grade operation, sitting within the broader Ethernet controller hierarchy: PHY -> transceiver -> network interface device -> communication IC -> semiconductor. Key features of the DP83848IVV include integrated 100BASE-TX/FX physical coding sublayer (PCS) and physical media attachment (PMA), 3.3V single-rail operation with 2.5V internal LDO, Auto-MDIX crossover detection, Energy Detect Plus power-down modes, and 4 kV ESD tolerance on the MDI pins. The device also features low-latency (sub-100ns) MII throughput, hardware pause-frame support for flow control, and an IEEE 1149.1 JTAG boundary-scan port for board test. The 48-LQFP package provides a thermally efficient surface-mount footprint with 31.4 C/W typical junction-to-ambient resistance. Architecture-wise, the DP83848IVV combines a DSP-based receive path with adaptive equalization to recover signals over >150m of CAT-5 cable, a 125 MHz PLL for 100BASE-TX clocking, and a 25 MHz crystal interface or external clock input. Internal voltage regulation simplifies power tree implementation by accepting a single 3.3V supply. The DP83848IVV is designed for industrial Ethernet nodes, factory automation controllers, motor drives with EtherCAT/PROFINET bridges, building-automation gateways, IP-based surveillance cameras, and any embedded MCU/MPU with MII/RMII needing 10/100 connectivity. Its -40C to +85C industrial temperature grade supports deployment in harsh environments. When designing with the DP83848IVV, follow TI's reference layout for the magnetics and 49.9 ohm 1% termination resistors as specified in the datasheet application section. Use a 25 MHz crystal or feed a clean external CMOS clock; keep the MDI traces length-matched within 50 mils and 100-ohm differential-impedance controlled for best EMI margin.
DP83848IVVX/NOPB - Industrial 10/100 Ethernet PHY | TI LQFP-48
The Texas Instruments DP83848IVVX/NOPB is a robust 10/100-Mbps Ethernet PHY transceiver (PHYTER) housed in a 48-pin LQFP (PT) package, designed for industrial temperature operation from -40C to +85C. It integrates MII/RMII/SNI MAC interfaces, supports both 100BASE-TX and 10BASE-T standards per IEEE 802.3u, and operates from a single 3.3 V supply. The device includes Auto-MDIX, hardware-driven cable diagnostics, and JTAG boundary-scan access, providing engineers with production-grade link visibility. An Ethernet PHY (physical layer transceiver) is the analog front-end that connects an MAC controller to the copper twisted-pair medium, performing encoding/decoding (MLT-3 for 100BASE-TX, Manchester for 10BASE-T), clock recovery, and adaptive equalization. PHYs sit at the bottom of the OSI physical layer and provide the digital baseband interface (MII/RMII/GMII) that links to the MAC. They are a sub-category of network interface ICs within the broader interface IC family, sitting between digital logic and the magnetics/connector of an Ethernet port. Key features include 3.3 V single-supply operation, integrated 100BASE-TX DSP with adaptive equalization and baseline-wander correction, programmable LED status outputs, IEEE 802.3u auto-negotiation, and a hardware Energy Detect power-down mode. The DP83848IVVX/NOPB ships with the SNI (Serial Network Interface) and JTAG test access port enabled, which simplifies board-level test and field diagnostics in factory-automation equipment. Architecturally, the part uses an DSP-based receive path with a 4B/5B/MLT-3 encoder-decoder and a PLL that recovers clock from inbound data. The integrated 1:1 turns-ratio magnetics interface and on-chip termination reduce external BOM count compared to legacy PHYs that required external termination networks, while the PT (LQFP-48) package gives a robust 0.5 mm pitch footprint suitable for industrial PCB assembly. Typical applications include industrial Ethernet switches, programmable logic controllers (PLCs), factory-automation nodes, motion-control drives, and embedded gateways requiring -40C to +85C operation. The wide temperature range and JTAG access make the part particularly attractive in Industry-4.0 retrofits where deterministic connectivity and field serviceability are required. When designing with this device, place the 50 ohm transmission-line impedance traces between PHY and magnetics to within 25 mm, and use the recommended 2 kV HBM-rated magnetics module to meet industrial ESD/Surge targets. Always verify the reference clock source stability, because MII jitter margins shrink as cable length approaches 100 m. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical layout notes not always aggregated in the manufacturer datasheet, so procurement and engineering teams can shortlist a known-good BOM faster.
DP83849IDVS - Dual-Port 10/100 Ethernet PHY | Texas Instruments
The Texas Instruments DP83849IDVS is a dual-port 10/100-Mbps Ethernet PHY transceiver with fiber support, industrial-temperature operation from -40°C to +85°C, and an 80-pin TQFP package measuring 12 mm by 12 mm. The device provides two independently managed Ethernet physical-layer channels for copper and fiber links, making it suitable for industrial networking equipment requiring more than one 10/100-Mbps port. An Ethernet PHY is a physical-layer transceiver that converts digital data into electrical or optical signaling suitable for network transmission and receives signals back into digital data. In the product hierarchy, the DP83849IDVS is an Ethernet PHY transceiver, a network interface IC, an integrated circuit, and a semiconductor. Its dual-port architecture supports equipment that needs redundant connectivity, management access, or simultaneous links within a single device. The verified manufacturer information identifies the DP83849IDVS as a dual-port 10/100-Mbps Ethernet PHY transceiver with fiber support. Its -40°C to +85°C industrial-temperature range supports deployment in factory automation, industrial control, communications equipment, and network infrastructure. The 80-pin TQFP package provides access to the PHY functions, power connections, management interfaces, and copper or fiber-related signaling required by the device. The dual-port configuration is the primary technical distinction. Two physical-layer channels can reduce the number of separate Ethernet PHY packages needed in a multi-port system, simplifying board allocation while preserving independent 10/100-Mbps operation. Detailed electrical characteristics, register functions, media interfaces, and internal architecture are not present in the supplied source excerpts and therefore remain subject to the complete manufacturer datasheet. Typical uses include industrial Ethernet switches, remote monitoring stations, factory-floor controllers, communications equipment, and network-interface modules. The DP83849IDVS is particularly relevant where two copper ports and fiber-capable connectivity must coexist in an industrial-temperature design. The manufacturer also identifies the DP83849IDIFVS-EVK as a related evaluation platform for dual industrial-temperature PHY operation with fiber support. Designers should verify the complete pin assignment, recommended transformer or magnetics interface, strap resistors, clocking requirements, and decoupling network against the manufacturer datasheet before layout. Because the supplied data identifies a 12 mm by 12 mm 80-pin TQFP package but does not provide the complete 80-pin pinout, the package drawing cannot be safely populated here. This page combines verified manufacturer and distributor information, pricing availability status, same-family alternatives, comparison parameters, and application guidance. It also distinguishes documented facts from engineering data that remains unavailable, helping engineers evaluate the DP83849IDVS without confusing approximate or unsupported specifications.
DP83858VF - 8-Port 100 Mb/s Ethernet Repeater | Texas Instruments
The Texas Instruments DP83858VF is a 100 Mb/s TX/T4 Repeater Interface Controller, also identified as 100RIC8, supporting up to eight 100 Mb/s Ethernet ports in a 132-PQFP package. The supplied data specifies a 4.75 V to 5.25 V supply range, 295 mA supply current, and IEEE 802.3 compatibility. An Ethernet repeater controller is an interface IC within the Ethernet networking hierarchy. It coordinates multiple 100 Mb/s network segments, regenerates and retimes received signals, and provides the control logic needed by low-port-count managed or unmanaged repeater systems. The DP83858 targets equipment that must extend Fast Ethernet connectivity across several ports without using eight separate external repeater controllers. The controller's defining features include support for as many as eight 100 Mb/s ports, 100 Mb/s TX/T4 operation, 5 V single-supply operation, and compatibility with the IEEE 802.3 repeater requirements identified in the manufacturer documentation. The 295 mA supply-current figure provides a basis for power budgeting, while the 132-PQFP mechanical format supports a substantial pin count for port-facing signals and control functions. The DP83858 belongs to the interface-controller category rather than a general-purpose transceiver. Its TX/T4 repeater architecture is intended for high-speed Ethernet systems and legacy Fast Ethernet infrastructure. Compared with a single-port PHY, the device concentrates repeater management and media-interface control for an eight-port system, reducing board-level component count while retaining a standardized networking architecture. Typical applications include managed Fast Ethernet switches, unmanaged low-port-count switches, Ethernet repeaters, industrial network concentrators, and legacy 100BASE-TX equipment. Installation requires careful PCB routing for high-speed differential pairs, solid supply decoupling, controlled return paths, and compliance with the manufacturer's recommended layout and termination practices. The main design trade-off is specialization: DP83858VF addresses multiport Fast Ethernet repeater control rather than modern multi-gigabit or single-port integrated PHYs. Legacy-system maintenance, industrial connectivity, and equipment replication are stronger reasons to select it than new high-bandwidth designs. This page consolidates the supplied manufacturer-related data, distributor listing, package information, and Ethernet application context. It also distinguishes verified specifications from parameters that require confirmation from the complete datasheet before schematic or PCB release.
DP83861VQM-3 - 10/100/1000 Ethernet PHY | Texas Instruments
Texas Instruments DP83861VQM-3 is a 10/100/1000M Ethernet physical-layer transceiver with integrated PMD sublayers and support for 10BASE-T, 100BASE-TX, and 1000BASE-T links. The device is supplied in a 208-PQFP package measuring 28 mm by 28 mm. The -3 ordering suffix identifies the grade, but further grade-specific electrical and environmental details require confirmation from the manufacturer datasheet. The DP83861 family is intended for systems that connect an Ethernet controller or digital processor to a copper network through an RJ45 magnetics interface. An Ethernet physical-layer transceiver, commonly called an Ethernet PHY, converts between digital MAC-layer data and analog signaling on twisted-pair cabling. Within the Ethernet hierarchy, the PHY operates below the MAC controller and above the physical medium. Its supported 10BASE-T, 100BASE-TX, and 1000BASE-T capabilities allow one physical interface to cover 10 Mb/s, 100 Mb/s, and 1000 Mb/s Ethernet operation. The associated GMII and MII interfaces connect the transceiver to the digital networking controller. The verified listing identifies the DP83861 as a full-featured Gigabit PHY that complies with IEEE 802.3u for 100BASE-TX and IEEE 802.3z/ab for 1000BASE-T Ethernet. It also identifies support for 10BASE-T operation. These protocol references establish the covered Ethernet generations, although individual timing, error, power, and link-performance limits are not present in the supplied source excerpts and are therefore marked for data confirmation rather than inferred. Typical implementations place the DP83861VQM-3 beside a network transformer and RJ45 connector, then connect its GMII or MII interface to an Ethernet MAC controller or communications processor. The large 208-pin PQFP provides a substantial mixed-signal interface, making careful grounding, controlled return paths, and high-speed differential routing important. Designers should separate analog PHY and magnetics-side return currents from digital processor and memory domains while observing the package and layout guidance in the manufacturer documentation. Applications include industrial Ethernet controllers, embedded gateways, network switches, test equipment, and communications modules requiring copper Ethernet connectivity. The part may also support migration paths from 10/100-Mb/s equipment to 1-Gb/s links when the complete PHY, transformer, connector, clocking, and firmware architecture can support the higher data rate. Automatic-negotiation details, supported media categories, cable reach, and media-access configuration must be confirmed in the manufacturer datasheet before final design release. This page consolidates the supplied distributor listings, package information, protocol references, sourcing data, and engineering guidance into a structured component record. It distinguishes verified facts from parameters that remain unavailable in the supplied excerpts. Any replacement decision should be based on pin-level comparison, media support, electrical limits, clock requirements, firmware register compatibility, and PCB-level validation rather than package naming alone.
DP83865BVH - 8/8 Gigabit Ethernet PHY | Texas Instruments
The Texas Instruments DP83865BVH is an 8/8 Gigabit Ethernet physical-layer transceiver with integrated support for 10BASE-T, 100BASE-TX, and 1000BASE-T operation, supplied in a surface-mount 128-pin PQFP package measuring 14 x 20 mm. Its verified operating supply information includes 1.8 V and 2.5/3.3 V rails, while its transceiver architecture connects an Ethernet MAC through a digital parallel interface to copper cabling. An Ethernet physical-layer transceiver, commonly called an Ethernet PHY, is the semiconductor layer that converts logical data transmitted by a network controller into electrical or optical signals suitable for a communications medium. Within the Ethernet hierarchy, a PHY sits below the MAC and above the physical medium. For copper Ethernet, the PHY handles encoding, signaling, clock recovery, link negotiation, and reception of data transmitted over twisted-pair cabling. The DP83865BVH is identified as an 8/8 transceiver, providing eight transmit and eight receive channels for parallel network-interface implementations. Verified source data identifies 10BASE-T and 100BASE-TX support and notes integrated PMD sublayers associated with 1000BASE-T operation. This makes the device relevant to multiport Ethernet switches, routers, network interface controllers, and industrial communication equipment requiring several copper ports. The 128-PQFP package is physically substantial compared with compact QFN Ethernet PHYs because it exposes a broad high-speed parallel interface, multiple PHY channels, supply rails, reference clocks, and copper-network connections. Its surface-mount construction supports automated assembly, but careful power-plane distribution, controlled clock routing, and high-speed signal-integrity management remain necessary in multi-channel Ethernet designs. Typical applications include 8-port Gigabit Ethernet switches, network interface cards, routers, industrial Ethernet equipment, and embedded communication systems. The 8/8 organization can reduce the number of discrete PHY devices required when several copper ports share one board, although system partitioning, thermal distribution, and magnetics selection must still be evaluated. For a new design, engineers should use the official Texas Instruments datasheet and pinout rather than assigning connections solely from generic Ethernet conventions. Verify every supply rail, transceiver channel, clock input, resistor network, magnetic-interface component, and exposed thermal or supply connection against that document before layout release. This page consolidates verified distributor specifications, package data, sourcing links, application context, and compatibility cautions. Its key information gain is the distinction between a true pin-to-pin replacement and a merely similar 8/8 Ethernet PHY, which prevents an electrically or mechanically invalid substitution.
DP83865DVH - 1G Ethernet PHY, 128-PQFP | Texas Instruments
The Texas Instruments DP83865DVH is a single-port Gigabit Ethernet physical-layer transceiver supporting 10BASE-T, 100BASE-TX, and 1000BASE-T in a 128-PQFP package measuring 14 x 20 mm. It operates from a 1.71 V to 1.89 V core supply and supports data rates through 1 Gbit/s. The commercial-temperature device is specified for 0 C to +70 C and has eight media-interface transmit or receive channels. An Ethernet PHY is the physical-layer component that converts digital Ethernet data supplied by a MAC into electrical signaling for a copper network, and receives analog signals from the cable. Within the Ethernet hierarchy, the PHY connects the digital MAC interface and the 10/100/1000BASE-T medium. This distinction matters because protocol handling remains above the PHY while the DP83865DVH performs line signaling, clock and data recovery, and physical-layer encoding functions. Verified source data identifies a 1 Gbit/s data rate, eight transceiver channels, a 1.71 V to 1.89 V supply range, approximately 430 mA supply current, and a 128-pin PQFP package. The device integrates physical medium-dependent sublayers required for 10BASE-T, 100BASE-TX, and 1000BASE-T Ethernet. Exact media-interface modes, clock tolerances, transceiver electrical limits, and pin-level functions are not present in the supplied search extracts and therefore require confirmation from the manufacturer datasheet before layout release. Typical implementation is a copper Gigabit Ethernet port in industrial controllers, embedded computers, test equipment, network interface cards, and communications hardware. The 128-PQFP footprint favors multilayer PCB routing and external magnetics rather than compact modules, while the 1.89 V maximum stated core supply requires a regulator with suitable headroom and power integrity. A network magnetics or integrated coupling arrangement is also required at the cable side, subject to the complete reference design. Engineers should preserve the exact interface voltage, termination, crystal or clock source, reset, and power-tree requirements given in the full DP83865 datasheet. Because no verified pricing schedule was supplied, unit prices remain marked as data needed rather than being inferred from generic distributor listings. The search data also indicates that no pin-to-pin DP83865 replacement is offered by TI, so substitution requires interface and PCB validation rather than an assumed footprint match. This page consolidates the verified distributor specifications, procurement sources, replacement evidence, and engineering cautions. It distinguishes confirmed electrical facts from unavailable details and avoids treating functionally similar PHYs as verified drop-in devices. That distinction is critical because Ethernet PHYs may use the same 128-pin package while differing in interface modes, strap behavior, clocking, register maps, and analog performance.
DP83867CRRGZT - Gigabit Ethernet PHY | Texas Instruments
Texas Instruments DP83867CRRGZT is a low-power, robust 10/100/1000 Base-TX Ethernet physical-layer transceiver with RGMII and SGMII interfaces, supplied in a 48-pin VQFN (RGZ) package. It supports 10BASE-T, 100BASE-TX, and 1000BASE-T operation and is designed to connect a digital Ethernet controller or processor to twisted-pair cabling. An Ethernet physical-layer transceiver, commonly called an Ethernet PHY, converts logical data transmitted by a media-access controller into electrical signals suitable for copper cabling. The PHY belongs to the network-interface hierarchy: Ethernet controller > Ethernet PHY > 10/100/1000 Base-T interface > physical-layer transceiver. Integrating the physical medium, physical coding, and physical data sublayers allows the host controller to communicate through standardized Ethernet protocols. The DP83867CRRGZT combines robust Gigabit Ethernet operation with low power consumption and a compact 48-VQFN package. Its RGMII and SGMII interfaces provide flexible connections to controllers with different internal architectures. The device also supports cable diagnostics, IEEE 1588 start-of-frame support, and JTAG 1149.1, according to the available manufacturer and comparison data. A 7 mm by 7 mm package supports compact industrial and network equipment designs. The CRRGZT ordering option is associated by the verified product information with a 48-pin VQFN (RGZ) package and an operating-temperature range of 0 °C to 70 °C. Its three principal operating supply voltages are 1.8 V, 2.5 V, and 3.3 V. Detailed electrical limits, clock requirements, register defaults, magnetic-component recommendations, and timing margins must be taken from the manufacturer datasheet before layout release. Typical applications include industrial Ethernet controllers, automated machinery, network switches, embedded Linux systems, test equipment, and industrial IoT gateways. The device is particularly relevant when a board needs 10/100/1000-Mbps copper Ethernet and the host controller supports RGMII or SGMII. For an RMII-only controller, the verified comparison information states that a bridging translator such as the Microchip LAN9354 is required. A critical design consideration is interface timing: RGMII clock and data paths must meet the required setup and hold windows, while the copper-channel magnetics, center taps, and termination network must follow the reference design. PCB layout should separate high-speed digital clocks from analog receive circuitry and provide a low-impedance, continuous return path beneath the PHY and magnetics. This page consolidates verified manufacturer and distributor information, supported PHY variants, interface-selection guidance, and practical integration considerations. It distinguishes documented facts from electrical details that still require confirmation from the current Texas Instruments datasheet, helping engineers evaluate the DP83867CRRGZT without relying on an unverified cross-reference listing.
DP83867CSRGZR - Gigabit Ethernet PHY RGMII/SGMII | Texas Instruments
Texas Instruments DP83867CSRGZR is a robust, low-power, fully featured Gigabit Ethernet Physical Layer transceiver (PHY) supporting 10BASE-Te, 100BASE-TX, and 1000BASE-T Ethernet protocols with RGMII and SGMII MAC interface options, packaged in a 48-pin VQFN (RGZ) 7x7 mm footprint. The device integrates the PMD sublayer and exceeds 8 kV IEC 61000-4-2 ESD (direct contact) immunity, targeting factory automation, motor drives, and other electrically harsh industrial environments. SGMII support enables seamless connection to MACs that lack parallel MII/GMII/RGMII pins, simplifying board routing on space-constrained designs. An Ethernet PHY (Physical Layer transceiver) is the analog front-end of an Ethernet link: it sits between the RJ45/magnetics on the line side and the MAC controller on the host side, performing PCS/PMA encoding, clock/data recovery, echo/ crosstalk cancellation, and link training. As a sub-class of network interface IC, the PHY falls under the broader hierarchy of networking ICs > interface ICs > integrated circuits. The DP83867CS series specifically targets the industrial Gigabit PHY niche where high ESD immunity, wide temperature support, and small form factor matter. Key features include configurable I/O voltage (3.3 V, 2.5 V, 1.8 V) for direct connection to FPGAs, SoCs, and ASICs of any logic family; ultra-low RGMII latency (TX < 90 ns, RX < 290 ns) which is essential for Time Sensitive Network (TSN) compliant systems; integrated cable diagnostics; and JTAG boundary scan support. The device ships in a 48-pin VQFN (RGZ) package with exposed thermal pad, and supports an extended industrial operating temperature range. The CS variant offers a low-power 457 mW typical operating power profile. Typical applications include industrial Ethernet switches, programmable logic controllers (PLCs), human-machine interfaces (HMIs), motor and motion control, factory automation backbones, and embedded networking on single-board computers. The wide operating temperature range and ESD robustness also make it well suited to outdoor PoE end-points and ruggedized IoT gateways where commercial-grade PHYs would be unreliable. Designers should refer to the manufacturer datasheet for the recommended magnetics, RJ45 integration, and reference clock selection, and should follow the IBIS model for SI-validated board layout.
DP83867CSRGZT - Robust GbE PHY, RGMII/SGMII, VQFN-48 | TI
The Texas Instruments DP83867CSRGZT is a low-power, robust, fully-featured Gigabit Ethernet Physical Layer transceiver with integrated PMD sublayers supporting 10BASE-Te, 100BASE-TX, and 1000BASE-T Ethernet protocols, offered in a 48-pin VQFN (RGZ) 7x7 mm package. Key headlines: 10/100/1000 Mbps operation, RGMII and SGMII MAC interface options, configurable I/O voltage (3.3 V, 2.5 V, 1.8 V), and an industrial-grade 0 C to 70 C operating range with TI's high-immunity PHY core. An Ethernet PHY (Physical Layer transceiver) is the analog/digital mixed-signal device sitting between a Media Access Controller (MAC) and the magnetics/RJ45 connector on a copper Ethernet link. The PHY handles line encoding/decoding (PAM-5 for 1000BASE-T, MLT-3 for 100BASE-TX), link training, echo cancellation, and cross-talk mitigation across four twisted pairs, while presenting a parallel or serial digital interface to the MAC. As a Physical Layer transceiver within the seven-layer OSI model, the PHY is part of the wired networking interface layer, and a critical power-management and signal-integrity IC in any embedded Ethernet design. Key features include cable diagnostics, low RGMII latency (TX < 90 ns, RX < 290 ns), Time-Sensitive Network (TSN) compliance, fast link drop mode, JTAG 1149.1 boundary scan support, and integrated PMD sublayers. The DP83867CS provides high ESD/EMC immunity and an ultra-low RGMII latency profile. Compared to integration assemblers using lower-immunity PHYs, the CS variant offers enhanced robustness for noisy industrial environments. Architecturally, the device uses TI's proprietary DSP-based echo canceller and baseline wander corrector across all four pairs, with auto-negotiation and Auto-MDIX, allowing direct connection to either a straight-through or crossover cable. The SGMII option reduces MAC-to-PHY pin count to four differential signals, freeing board area in space-constrained designs. Typical applications include industrial Ethernet switches, factory automation controllers, motor drives with EtherCAT/PROFINET support, building automation, and any embedded system requiring a small-footprint, low-power gigabit copper interface. The wide temperature range and immunity rating make the part especially suitable for industrial Ethernet switches and PLCs. When designing with this device, pay careful attention to MDI trace routing (100-ohm differential, length-matched within the pair), magnetics selection, and decoupling on each supply pin. Reference the TI DP83867 design checklist for layout guidance, especially the four-pair MDI routing and chassis-ground separation.
DP83867E - Gigabit Ethernet PHY, RGMII/SGMII, 48-VQFN | TI
The Texas Instruments DP83867E is a robust, low-power, fully-featured 10/100/1000 Mbps Ethernet Physical Layer transceiver with integrated PMD sublayers, supporting 10BASE-Te, 100BASE-TX, and 1000BASE-T Ethernet protocols, housed in a 48-pin VQFN (7x7 mm) package. The device delivers extra-low latency (TX < 90 ns, RX < 290 ns) and is offered in an industrial extended-temperature grade with SGMII and RGMII MAC interfaces. An Ethernet PHY (Physical Layer transceiver) is a mixed-signal IC that connects a MAC controller to the copper medium (twisted-pair cable), handling line encoding/decoding, link training, echo/next-crosstalk cancellation, and clock/data recovery across the MDI. The DP83867E sits at the bottom of the OSI physical layer, translating digital MAC frames into analog baseband signals on the cable. In the taxonomy: Ethernet PHY -> transceiver -> network interface IC -> communication semiconductor. The part exceeds 8 kV IEC 61000-4-2 ESD on the cable pins, making it a robust choice for industrial and automotive-grade Ethernet links. Key features include support for both RGMII and SGMII MAC interfaces, integrated 1.25 GHz SerDes for SGMII, low-power 1000BASE-T operation, programmable LED outputs, and a flexible MDIO/MDC management interface. The extended-temperature grade (-40C to +105C ambient with proper thermal design) targets industrial control, factory automation, and outdoor equipment where commercial-grade PHYs derate. Architecturally, the DP83867E uses a DSP-based echo and crosstalk canceller, an integrated 1000BASE-T PMA/PMD with on-chip termination, and a low-jitter PLL to recover the 125 MHz reference. The SGMII variant routes the recovered data over a 1.25 Gbps differential serial link, eliminating the 12-bit parallel RGMII bus and reducing board-layer routing complexity in space-constrained SoMs. Typical applications include industrial Ethernet switches, programmable logic controllers (PLCs), factory-floor IO modules, motor drives, telecom base-station routers, and automotive Ethernet PHYs for in-vehicle networking. The SGMII interface in particular suits SoCs that place the PHY on a remote daughter card or that prefer serial MAC connectivity. Design consideration: the MDI traces require 100-ohm controlled differential impedance and an integrated magnetics RJ-45 with center-tap; the 1.0 V analog and 2.5/3.3 V digital rails must be cleanly decoupled to meet the IEEE 802.3 return-loss mask. Use the TI reference design checklist for BOM and stack-up. This page synthesizes distributor pricing, package-accurate cross-references, and practical PCB design notes that go beyond the manufacturer datasheet to accelerate your Ethernet hardware bring-up.
DP83867ERGZR - 1GbE SGMII PHY | Texas Instruments
The Texas Instruments DP83867ERGZR is a single-port 10/100/1000BASE-T Ethernet physical-layer transceiver with RGMII and SGMII interfaces, supplied in a 48-pin VQFN RGZ package measuring 7 mm by 7 mm. It supports 1.0 V, 1.8 V, and 2.5 V supply options according to the verified distributor and comparison data. The extended-temperature ordering option operates from -40 °C to 105 °C, making the device suitable for industrial embedded networking and communications equipment that requires extended environmental coverage. An Ethernet physical-layer transceiver, commonly called an Ethernet PHY, is the circuit that converts digital Ethernet data between a MAC or communications processor and a physical copper network. The DP83867E belongs to the Gigabit Ethernet PHY hierarchy: Ethernet transceiver > physical-layer transceiver > PHY > semiconductor. Its 10BASE-T, 100BASE-TX, and 1000BASE-T support allows one physical network interface to accommodate 10 Mb/s, 100 Mb/s, and 1 Gb/s Ethernet operation, depending on the link negotiation and connected equipment. The verified ordering information identifies a 48-VQFN RGZ package, a 7 mm square land pattern, a 0.5 mm lead pitch, and a tape-and-reel shipping format. RGMII provides a parallel digital interface for a conventional MAC-to-PHY connection, while SGMII provides a high-speed serial interface for designs that benefit from fewer signal connections. The available comparison data also identifies cable-diagnostics, IEEE 1588 support of the stated SOF type, and JTAG 1149.1 among the notable device features. Because the DP83867ERGZR is specified as an extended-temperature, robust, low-latency Gigabit Ethernet PHY, it is relevant to industrial automation, motor-drive systems, embedded routers, test equipment, and communications infrastructure. These systems benefit from a compact 48-pin surface-mount package and flexible RGMII or SGMII host connectivity. The exact supported link rates, electrical characteristics, clocking requirements, media-access procedures, and recommended external circuitry must be confirmed against the manufacturer datasheet before a board design is released. A critical implementation consideration is that the PHY is part of a high-speed mixed-signal system. Designers should follow the manufacturer’s reference layout, provide the specified power and decoupling networks, and route high-speed differential pairs as controlled-impedance transmission lines. Magnetics, RJ45 circuitry, clock sources, reset timing, and the exact operating mode also require validation in the complete system rather than substitution based only on package similarity. This page consolidates the verified manufacturer and distributor information for DP83867ERGZR, adds application and design context, distinguishes documented facts from missing technical data, and evaluates only same-package drop-in candidates that can be traced to the supplied web results. It is intended to accelerate component screening while preserving the need for datasheet-level engineering verification before procurement or PCB release.
DP83867ERGZT - 1GbE SGMII PHY | Texas Instruments
The Texas Instruments DP83867ERGZT is a single-port 10/100/1000BASE-T Ethernet physical-layer transceiver with RGMII and SGMII host interfaces, extended-temperature capability, and a 48-VQFN 7 x 7 mm package. It supports 10BASE-T, 100BASE-TX, and 1000BASE-T protocols, integrates the required physical medium device sublayers, and connects directly to a transformer-based twisted-pair network interface. The device is specified for robust operation with ESD protection exceeding 8 kV under IEC 61000-4-2 direct-contact conditions. An Ethernet physical-layer transceiver, or Ethernet PHY, is the component that translates between a digital MAC-side interface and analog electrical signaling on a copper Ethernet cable. The DP83867 belongs to the interface-IC hierarchy and supports the physical layer for 10 Mb/s, 100 Mb/s, and 1 Gb/s Ethernet networks. Its RGMII and SGMII interfaces allow it to connect with a host processor, FPGA, network controller, or Ethernet switch subsystem while retaining compatibility with common copper-Ethernet infrastructure. Key features include support for all three standard copper Ethernet rates, simultaneous RGMII and SGMII interface options, a small 48-VQFN package, and a low-latency design intended for demanding communication equipment. The manufacturer describes the DP83867E as a robust, low-power, fully featured physical-layer transceiver. Its extended-temperature ordering option makes it suitable for industrial equipment and other installations where operating-temperature limits, reliability, and ESD immunity are important design considerations. The device integrates the PMD and PCS functions needed to interface with standard 10BASE-T, 100BASE-TX, and 1000BASE-T networks. Unlike a software-only MAC, the PHY performs the physical encoding, signaling, and recovery associated with copper Ethernet. The SGMII option is particularly useful when the PHY must connect across a serial high-speed digital interface, while RGMII provides a wider parallel interface for designs using a local processor or FPGA. Typical uses include industrial Ethernet switches, programmable logic controller gateways, factory automation controllers, network-attended test equipment, embedded systems, and rugged communications infrastructure. It is also appropriate for designs requiring a compact, single-port Gigabit Ethernet interface without the footprint of a larger multi-port transceiver. Designers should carefully follow the manufacturer reference layout for the exposed-pad package, provide the specified power and decoupling networks, and use a qualified Ethernet transformer with the required center-tap and termination arrangement. RGMII timing is especially sensitive to trace length and clock skew, while SGMII requires controlled impedance and low-jitter routing. Magnetics selection, isolation boundaries, grounding, and surge protection must be reviewed against the target installation environment. This product page consolidates manufacturer-supported functionality, verified distributor pricing, interface-focused comparisons, and practical Ethernet design guidance. It also distinguishes verified drop-in alternatives from pin-compatible parts that differ in package, temperature grade, register map, or interface support.
DP83867IRPAPT - Industrial GbE PHY, RGMII/GMII, 64-HTQFP | TI
The Texas Instruments DP83867IRPAPT is a robust, low-power, fully-featured gigabit Ethernet Physical Layer (PHY) transceiver with integrated PMD sublayers supporting 10BASE-Te, 100BASE-TX, and 1000BASE-T protocols, housed in a 64-pin HTQFP (PAP) 10x10 mm package. It delivers GMII, MII, and RGMII MAC interface support, an industrial temperature range of -40C to +85C, and ESD protection exceeding 8 kV IEC 61000-4-2 (direct contact). Full operating power is approximately 490 mW (PAP variant) and it includes cable diagnostics, IEEE 1588 Start of Frame Detection, and JTAG 1149.1 boundary scan. An Ethernet PHY (physical layer transceiver) is the lowest layer of the OSI model that converts digital MAC data into analog signaling for transmission over copper twisted-pair cable and recovers the analog signal at the receiving end. PHYs handle line coding (PAM-3 for 10BASE-Te, MLT-3 for 100BASE-TX, PAM-5 for 1000BASE-T), echo/next cancellation, equalization, and clock/data recovery. In the broader taxonomy, an Ethernet PHY is a type of network interface IC -> wired communication IC -> interface IC -> semiconductor. PHY choice (industrial temp, low latency, IEEE 1588 SOF) drives MAC selection, magnetics, and PCB stack-up decisions. The DP83867IRPAPT combines an integrated PHY with hardware timestamping (IEEE 1588 SOF), enabling sub-microsecond synchronization accuracy required by industrial Ethernet protocols such as EtherCAT, PROFINET, and TSN. The device supports both RGMII and GMII for flexible MAC attachment, including low-power mode down to approximately 230 mW (estimated from PAP data) when link is established. Cable diagnostics (TDR-based) detect open/short distance and polarity on each twisted pair, simplifying field installation. Typical applications include industrial Ethernet switches, programmable logic controllers (PLCs), industrial sensors and drives, factory automation gateways, and any embedded system requiring reliable GbE connectivity in harsh EMI/noisy environments. The industrial temperature rating and high ESD immunity make it well suited to factory floor equipment, motor drives, and outdoor installations where commercial-grade PHYs would fail. When designing in this part, allocate sufficient PCB area for the 64-HTQFP thermal pad and follow TI's reference layout for the magnetic interface. Use a 25 MHz reference clock or rely on the integrated 25 MHz crystal oscillator, and add proper decoupling (0.1 uF + 10 uF) near each supply pin to meet EMI/ESD margins. This page synthesizes distributor pricing, drop-in alternatives (same-brand first, then cross-brand), and practical PCB/thermal design notes not collected in any single distributor listing or in the manufacturer datasheet alone.
DP83867IRRGZ - Industrial GbE PHY, RGMII/SGMII, VQFN-48 | Texas Instruments
The Texas Instruments DP83867IRRGZ is a robust, low-power, fully featured Gigabit Ethernet physical layer (PHY) transceiver with integrated PMD sublayers supporting 10BASE-Te, 100BASE-TX, and 1000BASE-T over twisted-pair copper, housed in a 48-pin VQFN (RGZ) 7x7 mm package with exposed thermal pad. It features MAC interfaces of RGMII and SGMII, an industrial temperature range of -40C to +85C, and ESD protection that exceeds 8 kV IEC 61000-4-2 on the cable-side pins. The device targets harsh industrial Ethernet applications where EMI immunity, extended temperature, and long cable reach are required. An Ethernet PHY (Physical Layer transceiver) sits at layer 1 of the OSI model and converts digital MAC-side data into the analog differential signaling required by 10/100/1000BASE-T, while handling line coding, link training, echo/ crosstalk cancellation, and clock/data recovery. PHYs connect directly to an Ethernet MAC inside a switch controller, FPGA, SoC, or MCU, making them the physical bridge between the digital host and the RJ45/Magnetics front end. The DP83867 family belongs to the industrial-grade GbE PHY category, sitting above commercial-temperature PHY ICs and below automotive-qualified variants such as the DP83867IRRGZ-Q1. Key features include sub-1.5 W typical power consumption at gigabit speeds, integrated termination resistors, programmable LED drivers, IEEE 1588/SOF timestamping support, cable diagnostics (TDR), and a 25 MHz reference clock input. The RGMII/SGMII MAC interface gives the designer flexibility to bridge to either an FPGA/SoC with parallel RGMII pins or a serdes-based MAC with differential SGMII signaling. The wide 1.1 V / 2.5 V / 3.3 V supply rails simplify integration with mixed-voltage hosts, while the 8 kV ESD rating eliminates the need for external TVS arrays on the MDI pins in many designs. The internal architecture combines a DSP-based echo canceller and crosstalk canceller with an analog front-end optimized for 1000BASE-T PAM-5 signaling over 100 m of Cat5e/Cat6 cable. Auto-negotiation and Auto-MDIX streamline bring-up, while Energy-Efficient Ethernet (EEE) reduces idle power. Hardware diagnostics including cable length estimation and open/short detection assist field commissioning and predictive maintenance. Typical applications include industrial Ethernet switches, PLC communication modules, motor-control and servo-drive feedback links, factory-floor sensor backbones, ruggedized PoE PD/PoE+ powered devices, and embedded gateways that need deterministic GbE connectivity. The industrial temperature rating makes the part a standard choice for IEC 61131-2 / IEC 61850 environments. When designing with this PHY, place the 25 MHz crystal/oscillator within 50 mm of the XI/XO pins and keep the MDI differential pairs length-matched within 2 mm and referenced to a continuous ground plane. Add a 1 nF HV decoupling cap on each MDI center-tap and follow the reference schematic in the DP83867 datasheet for the RJ45 magnetics to pass IEEE conformance. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, accelerating PHY selection and PCB bring-up.
DP83867IRRGZR - Industrial GbE PHY, RGMII/SGMII, VQFN-48 | Texas Instruments (Tape & Reel)
The Texas Instruments DP83867IRRGZR is a robust, low-power, fully featured Gigabit Ethernet physical layer (PHY) transceiver with integrated PMD sublayers supporting 10BASE-Te, 100BASE-TX, and 1000BASE-T over twisted-pair copper, housed in a 48-pin VQFN (RGZ) 7x7 mm package with exposed thermal pad. It features MAC interfaces of RGMII and SGMII, an industrial temperature range of -40C to +85C, and ESD protection that exceeds 8 kV IEC 61000-4-2 on the cable-side pins. The device targets harsh industrial Ethernet applications where EMI immunity, extended temperature, and long cable reach are required. An Ethernet PHY (Physical Layer transceiver) sits at layer 1 of the OSI model and converts digital MAC-side data into the analog differential signaling required by 10/100/1000BASE-T, while handling line coding, link training, echo/ crosstalk cancellation, and clock/data recovery. PHYs connect directly to an Ethernet MAC inside a switch controller, FPGA, SoC, or MCU, making them the physical bridge between the digital host and the RJ45/Magnetics front end. The DP83867 family belongs to the industrial-grade GbE PHY category, sitting above commercial-temperature PHY ICs and below automotive-qualified variants such as the DP83867IRRGZR-Q1. Key features include sub-1.5 W typical power consumption at gigabit speeds, integrated termination resistors, programmable LED drivers, IEEE 1588/SOF timestamping support, cable diagnostics (TDR), and a 25 MHz reference clock input. The RGMII/SGMII MAC interface gives the designer flexibility to bridge to either an FPGA/SoC with parallel RGMII pins or a serdes-based MAC with differential SGMII signaling. The wide 1.1 V / 2.5 V / 3.3 V supply rails simplify integration with mixed-voltage hosts, while the 8 kV ESD rating eliminates the need for external TVS arrays on the MDI pins in many designs. The internal architecture combines a DSP-based echo canceller and crosstalk canceller with an analog front-end optimized for 1000BASE-T PAM-5 signaling over 100 m of Cat5e/Cat6 cable. Auto-negotiation and Auto-MDIX streamline bring-up, while Energy-Efficient Ethernet (EEE) reduces idle power. Hardware diagnostics including cable length estimation and open/short detection assist field commissioning and predictive maintenance. Typical applications include industrial Ethernet switches, PLC communication modules, motor-control and servo-drive feedback links, factory-floor sensor backbones, ruggedized PoE PD/PoE+ powered devices, and embedded gateways that need deterministic GbE connectivity. The industrial temperature rating makes the part a standard choice for IEC 61131-2 / IEC 61850 environments. When designing with this PHY, place the 25 MHz crystal/oscillator within 50 mm of the XI/XO pins and keep the MDI differential pairs length-matched within 2 mm and referenced to a continuous ground plane. Add a 1 nF HV decoupling cap on each MDI center-tap and follow the reference schematic in the DP83867 datasheet for the RJ45 magnetics to pass IEEE conformance. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, accelerating PHY selection and PCB bring-up.
DP83869HMRGZR - High-Immunity Gigabit Ethernet PHY | TI
The Texas Instruments DP83869HMRGZR is an extended-temperature, high-immunity gigabit Ethernet PHY transceiver with integrated PMD sublayers, supplied in a 48-pin VQFN (RGZ) 7x7 mm package. It supports 10BASE-Te, 100BASE-TX, and 1000BASE-T copper protocols along with 1000BASE-X and 100BASE-FX fiber interfaces, operating from a 1.8V/2.5V/3.3V supply rail. An Ethernet PHY (Physical Layer transceiver) is the interface IC that connects a MAC (Media Access Controller) to the physical copper or fiber cable, handling line coding, link training, echo/return-loss compensation, and clock/data serialization. As part of the Physical Layer transceiver -> Ethernet transceiver -> Network Interface IC -> Power Management/Connectivity IC hierarchy, gigabit PHYs sit one layer below the MAC and one layer above the magnetics/RJ-45 (or SFP fiber cage), translating MII/GMII/RGMII parallel data into differential serial signals compliant with IEEE 802.3 10/100/1000BASE-T. Key features of the DP83869HMRGZR include: IEEE 802.3 10/100/1000 Mbps operation, integrated PMD sublayers for copper and fiber, RGMII/MII/GMII MAC interfaces, media-conversion between copper and fiber ports, AEC-Q100-qualified extended-temperature grade (-40C to +125C), low-latency cut-through mode, and 8 kV IEC 61000-4-2 ESD protection (direct contact). The 48-pin VQFN (RGZ) package exposes a thermal pad for heat dissipation and supports reflow soldering on standard industrial PCB processes. Architecturally, the DP83869HMRGZR integrates the entire physical coding sublayer (PCS), physical medium attachment (PMA), and physical medium dependent (PMD) blocks on-chip, eliminating the need for external PHY magnetics tuning circuits. The device supports both SGMI and RGMII host interfaces with selectable timing modes, and includes integrated termination resistors that simplify the BOM. Cable diagnostics, loopback modes, and jumbo-frame support extend its utility in industrial Ethernet switches. Typical applications include industrial Ethernet switches, factory automation controllers, motor-drive communication boards, 5G small-cell fronthaul, automotive Ethernet gateways, and fiber-to-copper media converters. The wide temperature and high immunity make it well suited for IEC 61000-4 industrial EMC environments where standard PHYs would fail conformance. When designing with this part, ensure the MDI traces are 100-ohm differential with controlled 50-ohm single-ended impedance, place the 1.8V/2.5V/3.3V decoupling capacitors within 2 mm of each supply pin, and use a 4-layer PCB with a continuous ground plane below the PHY to meet IEEE 802.3 return-loss masks. This page synthesizes distributor pricing, drop-in TI same-family alternatives, design notes, and an honest comparison against cross-brand gigabit PHYs - content not aggregated on any single manufacturer or distributor page.
DP83901AV - 5V Serial Network Controller | Texas Instruments
The Texas Instruments DP83901AV is a 5 V serial network interface controller, or SNIC, with 110 mA typical supply current in a 68-pin PLCC J-lead package measuring 25.13 mm by 25.13 mm. Designed for CSMA/CD local-area networks, the device supports Ethernet 10BASE5, Thin Ethernet 10BASE2, and twisted-pair Ethernet 10BASE-T implementations. A serial network interface controller is a semiconductor that coordinates data exchange between a host computer and an Ethernet physical layer. Within the network-interface hierarchy, it sits between host hardware or software drivers and a network-medium transceiver. The DP83901AV consolidates functions required to manage Ethernet packet transfer, addressing, access, and station communication while operating from a single 5 V supply. The verified source material identifies the DP83901AV as a microCMOS VLSI controller with a serial interface, 7 pF typical input capacitance, and 7 pF typical output capacitance under the stated test conditions. Its nominal 110 mA supply current makes board-level power planning important in systems that operate continuously. Commercial temperature grade and tray packaging are also identified in the verified component listings. Because the part targets legacy Ethernet standards, its strongest design roles are 10BASE5, 10BASE2, and 10BASE-T network-interface designs rather than modern switched Gigabit Ethernet equipment. A host processor must provide the required bus, interrupt, memory, and network-driver environment. Designers should also preserve the exact timing, signal-conditioning, and pin functions documented for this legacy controller. Typical implementation choices include industrial data acquisition, embedded test systems, service equipment, and legacy Ethernet adapters that require 10BASE-T connectivity. The controller can be paired with suitable transceivers, magnetics, isolation, clocks, and termination networks, but the external network interface must be selected independently because the verified data does not identify one specific companion-device BOM. The primary design consideration is availability and lifecycle validation. This is a mature Ethernet controller, so procurement should confirm current supply, manufacturer status, and traceability before a new design is released. Existing products should preserve the original schematic, timing, and firmware assumptions unless a replacement has been independently qualified. This page consolidates the verified package, supply, interface, and Ethernet data while separating unavailable specifications from established facts. It also records the lack of a verified drop-in replacement rather than presenting a functionally similar controller as a safe PCB substitute.
DP83902AVLJ - 5V Serial Network Controller | Texas Instruments
The Texas Instruments DP83902AVLJ is a serial network interface controller for twisted-pair networks, supplied in a 100-lead rectangular QFP package and operating from a 4.75 V to 5.25 V supply. Its listed characteristics include a serial interface, approximately 140 mA supply current, commercial temperature grade, and tray packaging. The device is described by Texas Instruments as an ST-NIC serial network interface controller and is categorized as an obsolete interface controller. A serial network interface controller is an integrated circuit that manages the communication path between a computer or embedded system and a network medium. In the product hierarchy, this controller belongs to interface ICs and ultimately to the broader semiconductor category. The DP83902AVLJ was designed around twisted-pair network connectivity, where a physical-layer transceiver is commonly paired with a controller. The controller handles network framing and data exchange, while the external transceiver performs signal encoding, reception, and electrical isolation from the copper medium. The DP83902AVLJ uses a 4.75 V minimum and 5.25 V maximum supply voltage, giving system designers a nominal 5 V operating rail. The verified distributor listing reports a supply current of 140 mA. Its 100-pin QFP package provides a substantial number of external connections, which is typical for legacy Ethernet controllers that require parallel host data paths, address and control signals, clocking, interrupt signaling, and twisted-pair transceiver interfaces. Package dimensions, pin names, operating-temperature limits, Ethernet data rate, transceiver interface details, and electrical timing limits are not included in the supplied verification data. The DP83902AVLJ is most relevant to legacy networking equipment, industrial control systems, embedded controllers, and industrial Ethernet designs that already use this controller and its associated application circuitry. It should not be assumed interchangeable with a modern Ethernet controller merely because both perform networking functions. The verified cross-reference material specifically states that the STMicroelectronics SERC816/TR is not a direct drop-in replacement because its pinout, internal biasing, and MII timing characteristics differ. A PCB replacement therefore requires a detailed electrical, timing, and pin-level review rather than a simple component substitution. This page consolidates the verified distributor specifications, lifecycle information, sourcing details, and replacement constraints for DP83902AVLJ. Pricing is presented as unavailable because the verified sources provide quote or request-for-quotation terms rather than numeric unit prices. The pin table records all 100 package terminals but marks individual terminal names as unavailable rather than guessing pin functions. Engineers should obtain the manufacturer datasheet and original design reference before layout changes, firmware updates, or obsolescence redesigns.
DP83905AVQB - 10BASE-T Ethernet Controller | Texas Instruments
The Texas Instruments DP83905AVQB is an AT/LANTIC AT local-area-network twisted-pair interface controller with an integrated IEEE 802.3 10BASE-T PHY, an ISA interface, and a 160-pin QFP package measuring 28 mm by 28 mm. It operates from a single 4.75 V to 5.25 V supply and is specified for 0 °C to 70 °C commercial-grade operation. An Ethernet controller integrates the digital protocol, media-access, and physical-layer functions needed to connect a legacy personal computer or embedded ISA bus to a 10BASE-T twisted-pair network. The DP83905 supports the AT/LANTIC protocol family, IEEE 802.3 operation, and 10BASE-T signaling. Because the physical layer is integrated, a compliant design can use the controller with the appropriate line-driver, filter, isolation, and magnetics interface rather than implementing the complete PHY separately. Verified device attributes include a 4.75 V to 5.25 V supply range, nominal 100 mA supply current, IEEE 802.3 network support, 10BASE-T PHY operation, ISA host interfacing, a commercial temperature grade of 0 °C to 70 °C, and a 160-BFQFP package. The device is identified as obsolete in the supplied manufacturer-related documentation, so it is most appropriate for maintenance of legacy AT-compatible networking equipment rather than new mass-production designs. The DP83905AVQB belongs to the former National Semiconductor controller portfolio now served by Texas Instruments. Its large 160-pin gull-wing QFP construction is characteristic of late-1980s and early-1990s PC interface controllers, when integrating the AT bus logic, network controller, and 10BASE-T PHY into one device reduced component count and simplified legacy adapter-card design. Typical uses include industrial legacy controllers, AT-compatible Ethernet adapters, embedded data-acquisition systems, and repair or obsolescence-management programs for installed networking equipment. The ISA interface and 10BASE-T speed make the device most suitable for systems that already rely on the AT/LANTIC environment; it is not a modern 100BASE-TX or gigabit Ethernet controller. When replacing this component, engineers should verify the complete 160-pin footprint, exposed pad requirements, power rails, oscillator components, magnetics isolation, and legacy bus termination before substituting. Because this part is obsolete and few verified pin-compatible replacements are documented, board-level redesign to a current Ethernet controller may be safer than assuming equivalent availability.