EP1M350B780C6 vs EP1M350F780C5ES השוואה
השוואה מפורטת זה לצד זה של EP1M350B780C6 מאת Altera ו EP1M350F780C5ES מאת Altera. השווה מפרטים עיקריים, פרמטרים חשמליים, אריזה, סטטוס מחזור חיים, תמחור וזמינות כדי לקבוע את הרכיב הטוב ביותר לדרישות העיצוב שלך.
השוואת מפרטים
| פרמטר | EP1M350B780C6 | EP1M350F780C5ES |
|---|---|---|
| מותג | Altera | Altera |
| קטגוריה | FPGA & CPLD | FPGA & CPLD |
| סטטוס מחזור חיים | NRND | Obsolete |
| Manufacturer | Altera Corporation (now Intel FPGA) | — |
| Family | Mercury PLD | Mercury (EP1M) |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Typical Gate Count | 350,000 gates | — |
| Logic Elements | [DATA_NEEDED: logic element count] | — |
| Embedded Memory (EAB) | [DATA_NEEDED: EAB count and total RAM bits] | — |
| Phase-Locked Loops (PLLs) | [DATA_NEEDED: PLL count] | — |
| מארז | 780-pin FineLine BGA | 780-pin FC-FBGA (Flip-Chip BGA) |
| User I/O Pins (approx.) | 488 | — |
| Speed Grade | -6 | — |
| טמפרטורת פעולה | Commercial (0 C to +85 C) [DATA_NEEDED: explicit Tj range] | 0C to +85C (commercial) |
| Supply Voltage (Core) | [DATA_NEEDED: VCCINT] | — |
| Supply Voltage (I/O) | [DATA_NEEDED: VCCIO] | — |
| I/O Standards | LVTTL, LVCMOS, LVDS (per family datasheet) | — |
| Embedded Transceivers | High-speed serial transceivers (Mercury family feature) | — |
| Peak Reflow Temperature | 220 C (per distributor records) | — |
| סוג הרכבה | Surface Mount (BGA) | Surface Mount (BGA) |
| רמת MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| סטטוס RoHS | [DATA_NEEDED: lead-free / RoHS classification] | — |
| Programming Interface | JTAG (IEEE 1149.1) + Altera passive serial/AS modes | — |
| Tool Flow | Quartus II / MAX+PLUS II (Altera legacy) | — |
| Datasheet File Size | 869 Kbytes (per Alldatasheet index) | — |
| Datasheet Page Count | 86 pages (per Alldatasheet index) | — |
| Logic Elements / Cells | — | 14,400 |
| Equivalent System Gates | — | 350,000 |
| Core Voltage (VCCINT) | — | 1.71 V to 1.89 V (1.8 V nominal) |
| Transceivers | — | Integrated high-speed SERDES with CDR |
| Transceiver Data Rate | — | Up to 1.25 Gbps per channel |
| I/O Voltage Banks | — | Multiple, supporting mixed-voltage interfaces |
| Package Dimensions | — | 29 mm x 29 mm |
| Architecture | — | LUT-based with embedded CDR transceivers |
| Compliance | — | RoHS (per distributor listing; status: unknown) |
| Lead-Free | — | yes |