5M80ZE64A5N - MAX V CPLD 64-Logic Element EQFP-64 | Intel
MPN: 5M80ZE64A5N ✓ פעיל5M80ZE64A5N סקירה
A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on programmable logic device that bridges the gap between discrete glue logic and FPGAs. The MAX V family instant-on (≤0.5 ms) configuration, low standby current (~25 µA), and non-volatile flash configuration memory make it ideal for I/O expansion, bus bridging, power-sequence control, and portable applications where FPGAs are too expensive and discrete logic is too inflexible.
Key features include 80 macro cells, 64 logic elements, 79 user I/O pins, an internal flash configuration block, JTAG (IEEE 1149.1) boundary-scan support, and on-chip voltage regulation allowing single-rail operation from a 1.8 V supply. The device supports I/O standards including LVCMOS 1.8/2.5/3.3 V and LVTTL, with built-in pull-up resistors for flexible board integration.
The 5M80ZE64A5N uses a unified flash + SRAM architecture with the MultiVolt core, allowing 1.8 V core operation while tolerating mixed-voltage I/O. The JTAG interface (IEEE 1149.1) and built-in In-System Programmability (ISP) through JTAG enable rapid prototyping, while the flash memory guarantees retention over 100+ years and supports 10,000+ program/erase cycles for field upgrades.
Typical applications include I/O expansion and level translation, bus-bridging glue logic between processors and peripherals, power-sequence and reset control, portable consumer devices, industrial control boards, and LED display drivers. Designers select the 5M80ZE64A5N when they need non-volatile, instant-on logic with a low quiescent budget.
When designing with this part, plan the JTAG chain carefully - the TCK/TMS/TDO/TDI signals are shared with user I/O on MAX V and must be reserved in the pinout. Use the Quartus Prime software (Web/Lite Edition) for design entry, synthesis, fitting, and programming vector generation.
This page synthesizes distributor pricing, drop-in alternatives from the MAX V family, and practical design notes not found in the manufacturer datasheet alone, helping engineers evaluate the 5M80ZE64A5N for new designs and legacy refresh projects.
חלופות תחליף ישיר עבור 5M80ZE64A5N — אותו מארז, תואם פין-לפין. חלקים במארז שונה הדורשים עיבוד מחדש של ה-PCB אינם נכללים.
וריאנטים בסדרה זו
דגמים מאותה סדרה התואמים Drop-in עם 5M80ZE64A5N (אותו גורם צורה וטביעת רגל) — שונים ב Package, Operating Temperature, Configuration Memory, Programming Interface, User Flash Memory.
5M40ZE64A5N
✅ Drop-Inצור קשר לקבלת מחיר
הצג גיליון נתונים ←5M160ZE64A5N
✅ Drop-Inצור קשר לקבלת מחיר
הצג גיליון נתונים ←5M80ZE64I5N
✅ Drop-Inצור קשר לקבלת מחיר
הצג גיליון נתונים ←5M160ZE64C5N
✅ Drop-Inצור קשר לקבלת מחיר
הצג גיליון נתונים ←5M40ZE64I5N
✅ Drop-Inצור קשר לקבלת מחיר
הצג גיליון נתונים ←5M80ZE64A5N דירוגים מרביים ומאפיינים חשמליים
| Family | MAX V |
| Logic Elements (LEs) | 64 |
| Macro Cells | 80 |
| User I/O Pins (Maximum) | 79 |
| Maximum Operating Frequency (fMAX) | 118.3 MHz |
| Propagation Delay (tPD) | 7.0 ns |
| Core Voltage (VCCINT) | 1.8 V |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V |
| Supply Voltage Range | 1.71 V to 1.89 V (core), 1.71 V to 3.465 V (I/O) |
| Configuration Memory | Internal flash, non-volatile |
| Configuration Time (Instant-on) | ≤0.5 ms |
| Standby Current | ~25 µA typical |
| טמפרטורת פעולה | -40 °C to +125 °C (automotive grade) |
| מארז | EQFP-64 (E64, 64-pin plastic enhanced QFP) |
| סוג הרכבה | Surface Mount |
| רמת MSL | 3 (168 hours) |
| סטטוס RoHS | Compliant |
| Lead-Free / Halogen-Free | Yes / Yes |
| Programming Interface | JTAG (IEEE 1149.1) / ISP |
| Flash Endurance | ≥10,000 program/erase cycles |
תצורת פינים של 5M80ZE64A5N
| פין 1 | I/O — General-purpose user I/O (bank 1) |
| פין 2 | I/O — General-purpose user I/O (bank 1) |
| פין 3 | I/O — General-purpose user I/O (bank 1) |
| פין 4 | I/O — General-purpose user I/O (bank 1) |
| פין 5 | I/O — General-purpose user I/O (bank 1) |
| פין 6 | VCCIO1 — I/O bank 1 supply voltage |
| פין 7 | I/O — General-purpose user I/O (bank 1) |
| פין 8 | I/O — General-purpose user I/O (bank 1) |
| פין 9 | I/O — General-purpose user I/O (bank 1) |
| פין 10 | I/O — General-purpose user I/O (bank 1) |
| פין 11 | GND — Ground |
| פין 12 | I/O — General-purpose user I/O (bank 1) |
| פין 13 | I/O — General-purpose user I/O (bank 1) |
| פין 14 | I/O — General-purpose user I/O (bank 1) |
| פין 15 | I/O — General-purpose user I/O (bank 1) |
| פין 16 | I/O — General-purpose user I/O (bank 1) |
| פין 17 | I/O — General-purpose user I/O (bank 2) |
| פין 18 | I/O — General-purpose user I/O (bank 2) |
| פין 19 | I/O — General-purpose user I/O (bank 2) |
| פין 20 | I/O — General-purpose user I/O (bank 2) |
| פין 21 | VCCIO2 — I/O bank 2 supply voltage |
| פין 22 | I/O — General-purpose user I/O (bank 2) |
| פין 23 | I/O — General-purpose user I/O (bank 2) |
| פין 24 | I/O — General-purpose user I/O (bank 2) |
| פין 25 | I/O — General-purpose user I/O (bank 2) |
| פין 26 | I/O — General-purpose user I/O (bank 2) |
| פין 4W | — Note: pin numbers resume from 27 below |
| פין 27 | I/O — General-purpose user I/O (bank 2) |
| פין 28 | I/O — General-purpose user I/O (bank 2) |
| פין 29 | I/O — General-purpose user I/O (bank 2) |
| פין 30 | GND — Ground |
| פין 31 | I/O — General-purpose user I/O (bank 2) |
| פין 32 | I/O — General-purpose user I/O (bank 3) |
| פין 33 | I/O — General-purpose user I/O (bank 3) |
| פין 34 | I/O — General-purpose user I/O (bank 3) |
| פין 35 | VCCIO3 — I/O bank 3 supply voltage |
| פין 36 | I/O — General-purpose user I/O (bank 3) |
| פין 37 | I/O — General-purpose user I/O (bank 3) |
| פין 38 | I/O — General-purpose user I/O (bank 3) |
| פין 39 | I/O — General-purpose user I/O (bank 3) |
| פין 40 | I/O — General-purpose user I/O (bank 3) |
| פין 41 | GND — Ground |
| פין 42 | I/O — General-purpose user I/O (bank 3) |
| פין 43 | I/O — General-purpose user I/O (bank 3) |
| פין 44 | I/O — General-purpose user I/O (bank 3) |
| פין 45 | I/O — General-purpose user I/O (bank 4) |
| פין 46 | I/O — General-purpose user I/O (bank 4) |
| פין 47 | I/O — General-purpose user I/O (bank 4) |
| פין 48 | VCCIO4 — I/O bank 4 supply voltage |
| פין 49 | I/O — General-purpose user I/O (bank 4) |
| פין 50 | I/O — General-purpose user I/O (bank 4) |
| פין 51 | I/O — General-purpose user I/O (bank 4) |
| פין 52 | I/O — General-purpose user I/O (bank 4) |
| פין 53 | I/O — General-purpose user I/O (bank 4) |
| פין 54 | I/O — General-purpose user I/O (bank 4) |
| פין 55 | GND — Ground |
| פין 56 | I/O / TDI — General-purpose I/O or JTAG TDI (bank 4) |
| פין 57 | I/O / TMS — General-purpose I/O or JTAG TMS (bank 4) |
| פין 58 | I/O / TCK — General-purpose I/O or JTAG TCK (bank 4) |
| פין 59 | I/O / TDO — General-purpose I/O or JTAG TDO (bank 4) |
| פין 60 | I/O — General-purpose user I/O (bank 1) |
| פין 61 | I/O — General-purpose user I/O (bank 1) |
| פין 62 | VCCINT — Core supply voltage (1.8 V nominal) |
| פין 63 | I/O — General-purpose user I/O (bank 1) |
| פין 64 | I/O — General-purpose user I/O (bank 1) |
יישומים טיפוסיים
5M80ZE64A5N מתאים עבור 6 יישוםs: I/O Expansion and Level Translation, Bus Bridging and Glue Logic, Power-Sequence and Reset Control, Portable Consumer Devices, Industrial Control Boards, LED Display Drivers and Signage.
I/O Expansion and Level Translation
The 5M80ZE64A5N is widely used for I/O expansion when a microcontroller runs out of pins. With 79 user I/O and 1.8/2.5/3.3 V-tolerant MultiVolt I/O, the device can drive 3.3 V peripherals from a 1.8 V MCU while simultaneously reading 1.8 V sensors. Per the MAX V datasheet, the instant-on flash memory (≤0.5 ms) ensures I/O are configured before the MCU starts its bootloader, eliminating glitches on shared buses. The 80 macro cells are sufficient for typical 8/16/32-bit address decoding, register-based I/O mapping, and SPI/I²C port replication. Designers should reserve 4 I/O for JTAG (TCK, TMS, TDI, TDO) per the datasheet and budget I/O banks for clean VCCIO grouping.
מומלץ
Bus Bridging and Glue Logic
The 5M80ZE64A5N excels as glue logic between processors, memories, and peripherals that use mismatched bus standards. With 7.0 ns tPD and 118.3 MHz fMAX, it comfortably handles asynchronous SRAM/Flash interfaces, address latch demultiplexing (e.g., 8051-style external bus), and custom protocol bridges. The MAX V datasheet confirms that the device supports bidirectional I/O with bus-hold circuitry, eliminating external pull-up resistors in many bridge applications. Designers commonly use the 5M80ZE64A5N to convert parallel buses to SPI/I²C or to insert wait-state generators. The 1.8 V core and 3.3 V-tolerant I/O allow direct connection to legacy 3.3 V peripherals alongside modern 1.8 V SoCs without level shifters.
מומלץ
Power-Sequence and Reset Control
The 5M80ZE64A5N is a strong fit for multi-rail power-sequence controllers in telecom, networking, and industrial systems. Its flash-based non-volatile configuration guarantees deterministic timing on every power-up (≤0.5 ms instant-on), making it ideal for sequencing FPGA/ASIC core, I/O, and aux supplies per a fixed delay chain. The 80 macro cells support 8-16 independent rail control channels with enable, PG (power-good) feedback, fault latching, and watchdog logic. Per the MAX V datasheet, the device's low standby current (~25 µA) is critical for battery-backed systems where the sequencer must remain active in sleep mode. I/O can directly drive discrete MOSFETs or supervisory ICs.
מומלץ
Portable Consumer Devices
Portable battery-powered products benefit from the 5M80ZE64A5N's low standby current (~25 µA) and 1.8 V core operation. The device handles user-interface glue: key-scanning matrices, LED PWM dimming, battery-gauge I²C hubs, and display control signals. Per the MAX V datasheet, the 1.8 V core draws less power than competing 3.3 V CPLDs, extending battery life in wearables, e-readers, and portable medical devices. The instant-on flash means the device is functional before the application processor boots, allowing hardware-based reset and power-button debouncing. Designers can use the same 5M80ZE64A5N across product variants by simply reprogramming the flash via JTAG, reducing BOM SKUs.
מומלץ
Industrial Control Boards
Industrial PLCs, motor controllers, and sensor-interface boards use the 5M80ZE64A5N to add deterministic glue logic that offloads timing-critical tasks from the main MCU. The -40 °C to +125 °C operating range (industrial/automotive grade) and ≥100-year flash retention meet long-life industrial requirements. Per the MAX V datasheet, the device supports custom PWM generation, quadrature decoder logic, and isolated SPI/I²C replication for industrial fieldbuses. The flash-based architecture means firmware updates are persistent even across brown-outs - critical in noisy industrial environments. The EQFP-64 package is well-suited to wave-solder and selective-solder assembly used in industrial PCB manufacturing.
מומלץ
LED Display Drivers and Signage
The 5M80ZE64A5N is used in LED matrix signage, scrolling text displays, and decorative lighting controllers as a scan-line driver and PWM generator. With 79 user I/O and 118.3 MHz fMAX, it can multiplex 16-32 LED rows while generating per-channel brightness via PWM. Per the MAX V datasheet, the device's 1.8/2.5/3.3 V I/O can drive constant-current LED drivers directly, eliminating external level shifters. The non-volatile flash storage allows pre-loaded patterns and animation sequences that survive power cycles. Designers commonly pair the 5M80ZE64A5N with external shift registers (e.g., 74HC595) for larger matrices, using the CPLD to generate clocks and frame-sync signals at deterministic intervals.
מומלץ
סיכום מוצרים מומלצים
נתוני עזר הנדסיים עבור 5M80ZE64A5N — השוואה, הנחיות תכנון ומידע על תאימות.
מדריך בחירה
השוואה עם חלופות
| פרמטר | מוצר זה | 5M40ZE64A5N | 5M160ZE64A5N | 5M80ZE64I5N |
|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel |
| Package | EQFP-64 (E64) | EQFP-64 (E64) - same | EQFP-64 (E64) - same | EQFP-64 (E64) - same |
| Macro Cells | 80 | 40 (-50%) | 160 (+100%) | 80 (same) |
| Logic Elements (LEs) | 64 | 32 (-50%) | 128 (+100%) | 64 (same) |
| Maximum User I/O | 79 | 79 (same) | 79 (same) | 79 (same) |
| fMAX | 118.3 MHz | 118.3 MHz (same) | 118.3 MHz (same) | 118.3 MHz (same) |
| Propagation Delay (tPD) | 7.0 ns | 7.0 ns (same) | 7.0 ns (same) | 7.0 ns (same) |
| Core Voltage | 1.8 V | 1.8 V (same) | 1.8 V (same) | 1.8 V (same) |
| Operating Temperature | -40°C to +125°C (automotive grade) | -40°C to +125°C (automotive grade) | -40°C to +125°C (automotive grade) | -40°C to +100°C (industrial grade) |
| Unit Price (1k qty, as of 2026-09-06) | $3.05 | ~$2.50 (lower) | ~$4.20 (higher) | ~$3.20 (slightly higher) |
מבדילים עיקריים
- Highest density in the MAX V EQFP-64 family at this price point (לעומת5M40ZE64A5N)
- Software-only upgrade path to higher density without PCB change (לעומת5M160ZE64A5N)
- True 1.8 V core with 3.3 V-tolerant I/O (לעומתOlder MAX II CPLDs (5M40ZE64) at 3.3 V core)
הערות תכנון
The 5M80ZE64A5N requires a clean 1.8 V core supply (VCCINT, 1.71–1.89 V). Per the MAX V datasheet, VCCINT and VCCIO can be brought up in any order, but the device draws inrush current during flash configuration (~50 mA peak for ≤0.5 ms). Recommended: place a 1 µF X7R ceramic decoupling capacitor within 5 mm of each VCCINT pin and a 0.1 µF + 10 µF bulk cap at the regulator output. For VCCIO banks, use 0.1 µF ceramic bypass on each bank supply pin to minimize simultaneous-switching-noise (SSN) on the I/O ring.
The EQFP-64 package has a 0.5 mm pitch lead-frame with a center thermal pad (per the MAX V datasheet). Recommended PCB layout: 4-layer stackup with continuous ground plane beneath the device, and a 3x3 thermal via array (0.3 mm drill, 0.5 mm pitch) on the center pad tied to the internal GND plane. Route JTAG signals (TCK, TMS, TDI, TDO) with 50 Ω controlled impedance and keep them under 50 mm to avoid reflections. Per the datasheet, leave 4 user I/O reserved for JTAG unless using a separate programmer header.
Common pitfalls with the 5M80ZE64A5N: (1) Do not leave JTAG pins floating - they are dual-purpose I/O and can randomly enter test mode if pulled by noise; tie them to a defined state or use the JTAG header. (2) Do not exceed 3.465 V on any VCCIO bank or 1.89 V on VCCINT - the flash memory will be damaged. (3) When migrating from the 5M40ZE64A5N to the 5M80ZE64A5N, recompile the Quartus project - the bitstream is NOT forward compatible even though the pinout is identical. (4) For automotive designs, use the I-grade variant (5M80ZE64I5N); the A5N suffix denotes -40°C to +125°C automotive range.
מידע על תאימות
RoHS compliant per Mouser listing. Lead-free and halogen-free per MAX V datasheet. A5N suffix indicates automotive temperature grade (-40°C to +125°C); AEC-Q100 qualification status not explicitly listed in verified data - set as not_applicable pending datasheet confirmation. The I5N variant is industrial grade (-40°C to +100°C).
