LAN9352/ML - 2-Port 10/100 Managed Ethernet Switch, SPI/SQI | Microchip
MPN: LAN9352/ML ✓ פעילLAN9352/ML סקירה
A managed Ethernet switch is a Layer-2 networking device that connects multiple Ethernet segments, performs MAC-based frame forwarding, and exposes configuration/management features such as VLANs, QoS, port mirroring, and statistics counters. The LAN9352 sits in the managed-fast-Ethernet-switch IC taxonomy: Ethernet switch -> Layer-2 switch -> managed switch -> integrated-PHY switch. Unlike an unmanaged switch, the LAN9352/ML allows the host MCU to program registers for traffic shaping, IGMP snooping, and storm control, which is critical for real-time industrial protocols and AV streaming.
Key features include two integrated 10/100 PHYs with HP Auto-MDIX, support for IEEE 802.1Q VLAN and 802.1p QoS priority, a 16-bit SPI/SQI host interface, optional I2C management, and 32 KB of internal packet buffer. The device operates across the commercial 0C to 70C temperature range and supports Energy Efficient Ethernet (EEE) idle patterns, making it suitable for power-sensitive embedded applications.
The LAN9352/ML uses Microchip's proprietary switch fabric and supports cut-through and store-and-forward modes, along with 1.5 KB per-port address table. Hardware-based QoS with four priority queues and a per-port rate limiter enable deterministic traffic shaping for industrial Ethernet, audio/video bridging (AVB), and PROFINET-style real-time protocols.
Typical applications include industrial Ethernet gateways, factory automation PLCs, building automation controllers, IP surveillance NVR/DVR switches, point-of-sale terminals, embedded web server appliances, and consumer smart-home hubs that need a low-BOM 2-port switch fabric. The integrated dual-PHY approach removes the need for an external Ethernet transformer-pair, shrinking PCB area.
When designing with this device, allocate at least 4-layer routing for the two 100BASE-TX differential pairs to maintain return loss. Place the 72-QFN exposed pad soldered to a continuous ground plane for thermal dissipation; a stitched via array under the EP is recommended. The host SPI/SQI clock can run up to 80 MHz - check MCU timing margin when the switch is in cut-through mode.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, plus a 5-question FAQ block for AEO citation.
חלופות תחליף ישיר עבור LAN9352/ML — אותו מארז, תואם פין-לפין. חלקים במארז שונה הדורשים עיבוד מחדש של ה-PCB אינם נכללים.
וריאנטים בסדרה זו
דגמים מאותה סדרה התואמים Drop-in עם LAN9352/ML (אותו גורם צורה וטביעת רגל) — שונים ב Package.
LAN9352I/ML
✅ Drop-Inצור קשר לקבלת מחיר
הצג גיליון נתונים ←LAN9352TI/ML
✅ Drop-In📋 חלופה להתייחסות (לא בקטלוג)
LAN9353/ML
✅ Drop-In ⚠️ מפרטים לא מאומתיםצור קשר לקבלת מחיר
הצג גיליון נתונים ←LAN9352/ML דירוגים מרביים ומאפיינים חשמליים
| פונקציה | 2-Port 10/100 Managed Ethernet Switch with integrated PHYs |
| Number of Ports | 2 |
| Interface (Host) | 16-bit SPI / SQI (Serial Quad I/O), optional I2C management |
| Ethernet Standard | 10/100 Base-T/TX IEEE 802.3 |
| Integrated PHYs | 2 (HP Auto-MDIX on each port) |
| מתח אספקה | 1.8 V to 3.3 V |
| Switch Features | VLAN (802.1Q), QoS (802.1p), IGMP snooping, port mirroring, storm control |
| Packet Buffer | 32 KB internal SRAM |
| MAC Address Table | 1.5 KB per port (8K entries shared across switch fabric) |
| Forwarding Modes | Store-and-Forward, Cut-Through |
| QoS Queues | 4 priority queues per port |
| טמפרטורת פעולה | 0C to +70C (commercial) |
| מארז | 72-QFN (10x10 mm) with exposed pad |
| סוג הרכבה | Surface Mount |
| רמת MSL | 3 |
| סטטוס RoHS | Compliant |
מדריך תצורת פינים של LAN9352/ML 72-qfn (10x10 mm) with exposed pad
תצורת פינים עבור LAN9352/ML (מארזת 72-qfn (10x10 mm) with exposed pad). מספרי פינים, פונקציות ותרשימי חיבורים מוגדרים ב-Datasheet של היצרן. יש לעיין בו לקבלת ה-footprint המדויק והנחיות הלחמה.
אין נתוני פריסת פינים מפורטים עבור LAN9352/ML.
עיינו ב- גיליון נתונים עבור תצורת פינים מלאה.
יישומים טיפוסיים
LAN9352/ML מתאים עבור 7 יישוםs: Industrial Ethernet Gateway, Building Automation Controller, IP Surveillance NVR/DVR, Point-of-Sale Terminal, Embedded Web Server Appliance, Consumer Smart-Home Hub, Audio/Video Bridging (AVB) Endpoint.
Industrial Ethernet Gateway
The LAN9352/ML fits industrial Ethernet gateways because its two integrated 10/100 PHYs with HP Auto-MDIX eliminate the need for an external PHY pair, while the SPI/SQI host bus connects directly to low-pin-count MCUs. Its 4-queue QoS and IEEE 802.1Q VLAN support enable deterministic traffic shaping required for PROFINET, EtherNet/IP, and Modbus TCP traffic. The 32 KB packet buffer prevents frame drops during burst traffic from PLC scan cycles. Placed between the host MCU and two RJ45 ports, the switch handles Layer-2 forwarding autonomously, freeing the MCU for protocol processing.
מומלץ
Building Automation Controller
For BACnet/IP, KNX-IP, and Modbus TCP building automation systems, the LAN9352/ML provides the dual-port managed switch fabric required to daisy-chain field controllers. The 1.8V-3.3V supply matches low-power building automation MCUs, while the integrated PHYs reduce BOM cost. VLAN segmentation isolates security camera traffic from HVAC control traffic on the same physical switch. The commercial 0C-70C temperature range covers indoor installation scenarios, and the small 10x10 mm QFN footprint suits compact wall-mount controller enclosures.
מומלץ
IP Surveillance NVR/DVR
The LAN9352/ML works well in NVR/DVR recorders where two 10/100 ports are needed to isolate the camera LAN from the uplink WAN. Hardware-based QoS prioritizes recording traffic over background traffic, while port mirroring allows one port to be tapped for packet capture during diagnostics. The 32 KB packet buffer is large enough for typical 1080p H.264 streams at 4 Mbps, and the small 72-QFN footprint fits inside compact 1U NVR chassis. Energy Efficient Ethernet idle patterns reduce power when cameras are offline.
מומלץ
Point-of-Sale Terminal
POS terminals benefit from the LAN9352/ML's two-port managed switch, which separates the payment processor LAN from the back-office inventory network for PCI compliance. The integrated PHYs and 72-QFN footprint reduce BOM cost and PCB area, critical for compact POS form factors. VLAN tagging can isolate payment card data, and per-port rate limiting prevents unauthorized bandwidth use. The SPI/SQI host interface connects directly to common POS application processors, avoiding PCI bus complexity.
מומלץ
Embedded Web Server Appliance
The LAN9352/ML is well-suited for embedded web servers that expose a configuration portal on one port and connect to a corporate LAN on the other. The non-PCI SPI/SQI host interface is easy to drive from low-cost Cortex-M0/M3/M4 MCUs, while the integrated PHYs remove the need for an external Ethernet controller. The 32 KB packet buffer handles typical embedded web traffic (HTTP, REST, MQTT) without overflow. Commercial temperature range suits indoor appliance installations, and the 1.8V-3.3V supply matches energy-efficient MCUs.
מומלץ
Consumer Smart-Home Hub
Smart-home hubs often require a dual-port managed switch to connect the WAN uplink and a private device LAN. The LAN9352/ML fits this need with its small footprint, integrated PHYs, and 4-queue QoS for prioritizing voice assistant traffic. IEEE 802.1Q VLAN support isolates IoT devices from the home network, and IGMP snooping optimizes multicast traffic for IPTV or streaming services. The 1.8V-3.3V supply and low standby current are appropriate for always-on consumer devices, and the 72-QFN package fits compact hub enclosures.
מומלץ
Audio/Video Bridging (AVB) Endpoint
For AVB-compliant audio endpoints, the LAN9352/ML provides the Layer-2 managed switching foundation with 4-queue QoS that AVB streams require. The 32 KB packet buffer is sufficient for uncompressed 48 kHz/24-bit audio streams at 1 Mbps, while the hardware-based priority queues preserve the 802.1Qav timing requirements. The cut-through forwarding mode minimizes latency for time-sensitive audio traffic. The integrated HP Auto-MDIX PHYs reduce wiring constraints in consumer audio installations.
מומלץ
סיכום מוצרים מומלצים
נתוני עזר הנדסיים עבור LAN9352/ML — השוואה, הנחיות תכנון ומידע על תאימות.
מדריך בחירה
השוואה עם חלופות
| פרמטר | מוצר זה | LAN9352I/ML | LAN9352TI/ML | LAN9353/ML |
|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 72-QFN (10x10) | 72-QFN (10x10) - same | 72-QFN (10x10) - same | 72-QFN (10x10) - same |
| Number of Ports | 2 | 2 | 2 | 2 |
| Host Interface | 16-bit SPI/SQI | 16-bit SPI/SQI | 16-bit SPI/SQI | 16-bit SPI/SQI |
| Operating Temperature | 0C to +70C | -40C to +85C (industrial) | -40C to +85C (industrial) | 0C to +70C |
| Integrated PHYs | 2 (10/100 with HP Auto-MDIX) | 2 (10/100 with HP Auto-MDIX) | 2 (10/100 with HP Auto-MDIX) | 2 (10/100 with HP Auto-MDIX) |
| Packet Buffer | 32 KB | 32 KB | 32 KB | 32 KB |
| VLAN/QoS Support | 802.1Q VLAN, 802.1p QoS, 4 queues | 802.1Q VLAN, 802.1p QoS, 4 queues | 802.1Q VLAN, 802.1p QoS, 4 queues | 802.1Q VLAN, 802.1p QoS, 4 queues |
| Lifecycle Status | Active | Active | Active | Active |
מבדילים עיקריים
- Only 2-port managed switch with non-PCI 16-bit SPI/SQI host interface in 72-QFN (10x10) (לעומתKSZ8001LI)
- Industrial temperature grade available in same footprint (לעומתLAN9352I/ML)
- Hardware-based 4-queue QoS and 32 KB packet buffer (לעומתLAN9252/PT)
הערות תכנון
Route the two 100BASE-TX MDI differential pairs as 100-ohm differential traces on a 4-layer PCB with a continuous ground plane beneath them. Keep trace length matching within 50 mils to preserve return loss. Place the 1:1 magnetics within 25 mm of the RJ45 connector to minimize EMI. Stitch the LAN9352/ML exposed pad (EP) with a 5x5 via array to the inner ground plane for thermal dissipation - the EP is the primary heat path.
The LAN9352/ML requires a 1.8V to 3.3V supply; bulk-decouple the VDD pins with a 10uF tantalum or ceramic capacitor plus a 0.1uF ceramic bypass placed within 5 mm of each VDD pin. The integrated LDOs generate internal rails from the external supply, so only one external rail is needed. Add a ferrite bead on the analog AVDD supply pins to isolate digital switching noise from the sensitive PHY analog blocks.
Do not omit the 25 MHz reference clock or the 32.768 kHz clock if the switch is configured to use IEEE 1588 timing features - both are required for proper switch fabric operation. Verify the SPI/SQI clock polarity and phase against the host MCU's timing budget; running the host bus at 80 MHz requires the MCU to have sufficient setup/hold margin. Also, ensure the JTAG TDI/TMS/TCK pins are either driven or pulled to a defined state at reset to avoid latch-up.
Keep the 25 MHz crystal or oscillator within 5 mm of the LAN9352/ML XI/XO pins and shield the traces with a ground guard ring. The analog PHY ground (AGND) and digital ground (DGND) should be joined at a single point under the exposed pad to avoid ground loops that can degrade MDI return loss. Route the SPI/SQI host bus away from the MDI traces and clock signals to prevent crosstalk into the PHY receiver path.
מידע על תאימות
RoHS compliant per Microchip product page. Not AEC-Q100 qualified; choose LAN9352I/ML for industrial temperature range but it is still not automotive-grade.
