10AS048H1F34E1HG vs 10AS048H2F34E2LG तुलना
विस्तृत दोनों ओर की तुलना 10AS048H1F34E1HG द्वारा Altera और 10AS048H2F34E2LG द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Altera
10AS048H1F34E1HG - Arria 10 SX SoC FPGA, 480K LE, Dual A9, 1152-FBGA | Intel (Altera)
10AS048H1F34E1HG ✓ सक्रियIntel
10AS048H2F34E2LG - Arria 10 SX 480K SoC FPGA, Dual A9, 1152-FBGA | Intel
10AS048H2F34E2LG ✓ सक्रियविशेषता तुलना
| पैरामीटर | 10AS048H1F34E1HG | 10AS048H2F34E2LG |
|---|---|---|
| ब्रांड | Altera | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | सक्रिय | सक्रिय |
| Series | Arria 10 SX | — |
| Device Type | SoC FPGA (FPGA + ARM Cortex-A9 HPS) | — |
| Architecture | Hard Processor System (HPS) + Programmable Logic | — |
| Processor Core | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Logic Elements | 480K | 480000 |
| User I/O Count | 492 | — |
| Operating Frequency (HPS) | 1.5 GHz | — |
| पैकेज | 1152-FBGA, FC (35x35 mm) | 1152-ball FC-FBGA (F34), 35 x 35 mm |
| Process Technology | 20 nm | 20 nm |
| Temperature Grade | Industrial (E1) | — |
| RoHS स्थिति | Compliant (HG suffix) | Compliant |
| माउंटिंग प्रकार | Surface Mount (flip-chip BGA) | Surface Mount (flip-chip BGA) |
| Memory Interfaces | DDR3 / DDR4 with hard controllers | — |
| Transceivers | Multi-gigabit (per H1 grade) | [DATA_NEEDED: number / data rate] |
| DSP Blocks | Variable-precision DSP (per Arria 10 family) | [DATA_NEEDED: variable-precision DSP block count] |
| Family | — | Arria 10 SX |
| Core Voltage | — | 0.9 V |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 1.5 GHz |
| Operating Temperature Grade | — | Industrial / Medical (per OPN code H2) |
| Logic Family | — | Arria 10 SoC FPGA |
| Adaptive Logic Modules | — | [DATA_NEEDED: ALM count] |
| Embedded Memory (M20K) | — | [DATA_NEEDED: Mbits] |
| User I/O Banks | — | [DATA_NEEDED: bank count and total user I/O] |
| MSL स्तर | — | 3 (per FBGA package) |