5CSXFC6C6U23C8N vs 5CSXFC5C6U23C8N तुलना
विस्तृत दोनों ओर की तुलना 5CSXFC6C6U23C8N द्वारा Intel और 5CSXFC5C6U23C8N द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Intel
5CSXFC6C6U23C8N - Cyclone V SX SoC FPGA, 110K LE, ARM Cortex-A9 | Intel
5CSXFC6C6U23C8N ✓ सक्रियविशेषता तुलना
| पैरामीटर | 5CSXFC6C6U23C8N | 5CSXFC5C6U23C8N |
|---|---|---|
| ब्रांड | Intel | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | सक्रिय | सक्रिय |
| Family | Cyclone V SX (SoC FPGA) | Cyclone V SX |
| Series | Cyclone V SX | — |
| Architecture | MCU + FPGA (Hard Processor System + FPGA fabric) | — |
| Logic Elements | 110,000 | 85,000 |
| Process Technology | 28 nm low-power (TSMC) | 28 nm TSMC low-power |
| Core Voltage | 1.1 V | 1.1 V |
| Hard Processor System (HPS) | Dual-core ARM Cortex-A9 MPCore with CoreSight | — |
| Processor Maximum Frequency | 600 MHz | — |
| HPS L1 Cache | 32 KB instruction + 32 KB data per core | — |
| HPS L2 Cache | 512 KB shared | — |
| DSP Blocks | Variable-precision DSP (number not specified in retrieved data) | — |
| Embedded Memory | M10K blocks (total Kbits [DATA_NEEDED: total embedded memory Kbits]) | — |
| Transceivers | Up to 3.125 Gbps integrated transceivers | — |
| Maximum User I/O | 145 user I/O (per DigChip summary; full count per package [DATA_NEEDED: package pinout max user I/O]) | — |
| Memory Controller | Hard controller supporting DDR2, DDR3, LPDDR2 | — |
| पैकेज | 672-pin UFBGA (UBGA), 23x23 mm | 672-pin UBGAFBGA (23x23 mm) |
| माउंटिंग प्रकार | Surface Mount (BGA) | — |
| ऑपरेटिंग तापमान | -40C to +100C (industrial grade, code C) | 0 C to +85 C (commercial) |
| MSL स्तर | 3 (per JEDEC J-STD-020, typical for large BGA) | — |
| RoHS स्थिति | Compliant | — |
| Lead-Free / Halogen-Free | Yes (lead-free BGA; halogen status [DATA_NEEDED: halogen-free yes/no]) | — |
| Speed Grade | C8 (commercial speed grade 8) | C8 |
| Lifecycle | Active (Cyclone V family in production) | — |
| Device Variant | — | 5CSXFC5 (5CSXC5 logic density) |
| Logic Array Blocks (LABs) | — | 3,207 |
| Maximum User I/O Pins | — | 145 |
| HPS Processor Cores | — | Dual ARM Cortex-A9 MPCore |
| HPS Maximum Frequency | — | 600 MHz |
| Integrated Transceivers | — | 3.125 Gbps |
| Hard Memory Controller | — | DDR3 (HPS side) |
| Lead-Free / RoHS | — | Yes |