EP1810JI-45 vs EP1810JI-35 तुलना
विस्तृत दोनों ओर की तुलना EP1810JI-45 द्वारा Altera और EP1810JI-35 द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP1810JI-45 | EP1810JI-35 |
|---|---|---|
| ब्रांड | Altera | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Manufacturer | Altera (now Intel FPGA) | — |
| Series | Classic EPLD Family | — |
| Device Type | UV-Erasable / OTP Complex PLD | — |
| Macrocell Count | 48 | — |
| Maximum Operating Frequency | 33.3 MHz | — |
| Propagation Delay (tPD) | 50 ns | — |
| Configurable I/O Lines | 48 | — |
| Dedicated Inputs | 12 | 48 |
| Technology | CMOS EPROM | — |
| Package Code | QCCJ | — |
| Package Type | 68-pin JLCC (J-leaded ceramic chip carrier) | — |
| Terminal Form | J BEND | — |
| Package Shape | SQUARE | — |
| Number of Terminals | 68 | — |
| Temperature Grade | INDUSTRIAL | — |
| ऑपरेटिंग तापमान | -40 °C to +85 °C | -40C to +85C (Industrial) |
| सप्लाई वोल्टेज | 5 V (TTL compatible) | 5 V (typical classic EPLD) |
| Programming Method | UV-erase (windowed) / OTP via JEDEC | — |
| Device Family | — | Classic EPLD |
| Macrocells | — | 48 |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | -35 |
| पैकेज | — | 28-pin JLCC (J-leaded ceramic, windowed) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| माउंटिंग प्रकार | — | Through-Hole (J-lead) |
| RoHS स्थिति | — | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| MSL स्तर | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |