EP1S40F1020C5GA vs EP1S40F1020C5DM तुलना
विस्तृत दोनों ओर की तुलना EP1S40F1020C5GA द्वारा Intel और EP1S40F1020C5DM द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP1S40F1020C5GA | EP1S40F1020C5DM |
|---|---|---|
| ब्रांड | Intel | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Series | Stratix | Stratix |
| Logic Elements (LE) | 41,250 | — |
| Total RAM Bits | 3,423,744 | — |
| User I/O Count | 773 | 773 |
| पैकेज | 1020-BBGA (FineLine BGA) | 1020-ball FineLine BGA (33 mm x 33 mm, 1.0 mm pitch) |
| माउंटिंग प्रकार | Surface Mount | Surface Mount (BGA) |
| ऑपरेटिंग तापमान | 0C to +85C (Commercial) | 0C to +85C (commercial) |
| Speed Grade | C5 | — |
| Process Node | 0.13 µm CMOS with 9-layer metal | — |
| Supply Voltage (Core) | [DATA_NEEDED: VCCINT value] | — |
| I/O Bank Count | [DATA_NEEDED: bank count] | — |
| DSP Blocks | Embedded multiplier blocks (count per Stratix datasheet family) | 12 (up to 28.8 GMACS at 200 MHz) |
| PLL Count | Up to 12 enhanced PLLs (per Stratix family) | — |
| High-Speed Transceivers | Up to 12 channels (per Stratix family, variant dependent) | — |
| Configuration Method | JTAG, Passive Serial, Altera EPC device | — |
| RoHS स्थिति | Unknown - non-GA suffix commercial part | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes (per Altera/Intel policy at release) | — |
| MSL स्तर | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL level] |
| Product Type | — | FPGA - Field Programmable Gate Array |
| Logic Elements | — | 41,250 |
| Embedded Memory | — | 3,423 Kbits TriMatrix |
| Number of LABs/CLBs | — | 4125 |
| Number of PLLs | — | 6 (8 outputs each) |
| Number of Clock Networks | — | 16 |
| Core Voltage VCCINT | — | 1.5 V |
| I/O Voltage VCCIO | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) |
| Process Technology | — | 0.13 µm CMOS |
| Configuration Modes | — | PS, PPS, PPA, JTAG |