EP1S40F1020C5GA vs EP1S40F1020C5DM 比較
詳細並排比較 EP1S40F1020C5GA 由 Intel 與 EP1S40F1020C5DM 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1S40F1020C5GA | EP1S40F1020C5DM |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Series | Stratix | Stratix |
| Logic Elements (LE) | 41,250 | — |
| Total RAM Bits | 3,423,744 | — |
| User I/O Count | 773 | 773 |
| 封裝 | 1020-BBGA (FineLine BGA) | 1020-ball FineLine BGA (33 mm x 33 mm, 1.0 mm pitch) |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| 工作溫度 | 0C to +85C (Commercial) | 0C to +85C (commercial) |
| Speed Grade | C5 | — |
| Process Node | 0.13 µm CMOS with 9-layer metal | — |
| Supply Voltage (Core) | [DATA_NEEDED: VCCINT value] | — |
| I/O Bank Count | [DATA_NEEDED: bank count] | — |
| DSP Blocks | Embedded multiplier blocks (count per Stratix datasheet family) | 12 (up to 28.8 GMACS at 200 MHz) |
| PLL Count | Up to 12 enhanced PLLs (per Stratix family) | — |
| High-Speed Transceivers | Up to 12 channels (per Stratix family, variant dependent) | — |
| Configuration Method | JTAG, Passive Serial, Altera EPC device | — |
| RoHS 狀態 | Unknown - non-GA suffix commercial part | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes (per Altera/Intel policy at release) | — |
| MSL 等級 | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL level] |
| Product Type | — | FPGA - Field Programmable Gate Array |
| Logic Elements | — | 41,250 |
| Embedded Memory | — | 3,423 Kbits TriMatrix |
| Number of LABs/CLBs | — | 4125 |
| Number of PLLs | — | 6 (8 outputs each) |
| Number of Clock Networks | — | 16 |
| Core Voltage VCCINT | — | 1.5 V |
| I/O Voltage VCCIO | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) |
| Process Technology | — | 0.13 µm CMOS |
| Configuration Modes | — | PS, PPS, PPA, JTAG |