EP1S80F1020C6 vs EP1S30F1020C6 तुलना
विस्तृत दोनों ओर की तुलना EP1S80F1020C6 द्वारा Intel और EP1S30F1020C6 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP1S80F1020C6 | EP1S30F1020C6 |
|---|---|---|
| ब्रांड | Intel | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Series | Stratix | — |
| Logic Elements | 79,040 | 32470 |
| Total RAM Bits | 7,427,520 | 3317184 |
| Number of Logic Blocks / LABs | 9,191 | — |
| Number of I/O Pins (max) | 773 user I/O | — |
| Number of Pins / Balls | 1020 | — |
| Package Type | FC-FBGA (flip-chip fine-pitch BGA), 33 x 33 mm, 1.0 mm pitch | — |
| Process Technology | 130 nm CMOS | 0.13 micrometer SRAM, all-layer copper |
| Core Supply Voltage (VCCINT) | 1.5 V nominal (1.425 V to 1.575 V) | — |
| Speed Grade | C6 | 6 |
| Operating Temperature (Commercial) | 0 C to +85 C | — |
| माउंटिंग प्रकार | Surface Mount | Surface Mount |
| Maximum Internal Clock Frequency | 450.05 MHz | — |
| Family Description | FPGA - Field Programmable Gate Array | — |
| Embedded Memory | TriMatrix (three block sizes, true/simple dual-port) | — |
| Configuration Interface | JTAG (IEEE 1149.1) + serial/parallel configuration device | — |
| Design Tool | Quartus II (legacy, Stratix family) | — |
| RoHS स्थिति | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS Status] |
| नमी संवेदनशीलता स्तर (MSL) | [DATA_NEEDED: MSL rating] | — |
| Family | — | Stratix |
| Core Voltage | — | 1.5 V |
| DSP Blocks | — | 28 |
| Embedded Multipliers | — | Yes, 9-bit x 9-bit elements |
| User I/O Pins | — | 726 |
| पैकेज | — | 1020-ball FCBGA (BBGA) |
| Temperature Grade | — | Commercial (C) |
| Configuration Method | — | SRAM-based, JTAG boundary-scan |
| ऑपरेटिंग तापमान | — | 0C to +85C (commercial) |
| MSL स्तर | — | [DATA_NEEDED: MSL Level] |