EP1SGX10DF672C5N vs EP1S25F672C5N तुलना
विस्तृत दोनों ओर की तुलना EP1SGX10DF672C5N द्वारा Intel और EP1S25F672C5N द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Intel
EP1SGX10DF672C5N - Stratix GX FPGA, 10,570 Cells, 672-BGA | Intel
EP1SGX10DF672C5N ⚠ अंतिम खरीदविशेषता तुलना
| पैरामीटर | EP1SGX10DF672C5N | EP1S25F672C5N |
|---|---|---|
| ब्रांड | Intel | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | अंतिम बार खरीदें | Obsolete |
| Family | Stratix GX | Stratix |
| Logic Cells | 10,570 | — |
| Logic Array Blocks (LABs) | 1,057 | — |
| Configurable Logic Blocks | 1,200 | — |
| User I/Os | 362 | — |
| On-chip RAM | 920,448 bits | — |
| Supply Voltage (Core, VCCINT) | 1.5 V nominal (1.425 V to 1.575 V) | — |
| Technology | 130 nm CMOS | — |
| ऑपरेटिंग तापमान | 0 C to 85 C (Commercial) | — |
| पैकेज | 672-ball FC-FBGA (FineLine BGA), 33 x 33 mm, 1.0 mm pitch | — |
| माउंटिंग प्रकार | Surface Mount (Flip-Chip BGA) | Surface Mount (BGA) |
| Logic Family | CMOS | — |
| Configuration | Passive Serial / Passive Parallel / JTAG / Altera Serial | — |
| RoHS स्थिति | Compliant (FBGA package) | Compliant |
| High-Speed Transceivers | Embedded GX transceivers (data rate not specified in provided data [DATA_NEEDED: transceiver count and max data rate]) | — |
| Series | — | EP1S25 |
| Logic Elements (Cells) | — | 25,660 |
| Number of CLBs | — | 2,566 |
| Number of Logic Cells / Gates | — | [DATA_NEEDED: total system gates] |
| Process Technology | — | 130 nm CMOS |
| Maximum Internal Frequency | — | 500 MHz |
| Core Supply Voltage | — | 1.5 V (nominal) |
| Number of I/O Pins | — | 473 user I/O |
| Number of I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| Package Type | — | FineLine BGA (FBGA) |
| Package Pin Count | — | 672 |
| Ball Pitch | — | 1.00 mm |
| ऑपरेटिंग तापमान रेंज | — | 0 °C to +85 °C (commercial) |
| Speed Grade | — | C5 |
| Lead-Free (Pb-Free) | — | Yes (suffix "N") |
| Configuration Method | — | SRAM-based, programmable via JTAG / Passive Serial / Fast Passive Parallel |