EP20K1000CF672C7GZ vs EP20K1000CF33C9ES तुलना
विस्तृत दोनों ओर की तुलना EP20K1000CF672C7GZ द्वारा Intel और EP20K1000CF33C9ES द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Altera
EP20K1000CF33C9ES - APEX-20KC FPGA 1M Gates 38400 LE 1020-FBGA
EP20K1000CF33C9ES ⚠ अंतिम खरीदविशेषता तुलना
| पैरामीटर | EP20K1000CF672C7GZ | EP20K1000CF33C9ES |
|---|---|---|
| ब्रांड | Intel | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | अंतिम बार खरीदें |
| Family | APEX 20KC | APEX-20KC |
| Series | APEX-20KC® | — |
| Manufacturer | Intel (formerly Altera) | Intel (formerly Altera) |
| System Gates | 1,000,000 | — |
| Logic Elements / Cells | 38,400 | — |
| Total RAM Bits | 327,680 | — |
| Number of I/O | 508 | — |
| Number of LABs/CLBs | 2560 | — |
| Number of EABs | 160 | — |
| Number of Logic Elements per EAB | 2048 bits | — |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V | — |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| पैकेज / केस | 672-FBGA (672-BBGA) | — |
| Supplier Device Package | 672-FBGA (27x27 mm, 1.27 mm pitch) | — |
| माउंटिंग प्रकार | Surface Mount | — |
| Speed Grade | C7 (7 ns pin-to-pin delay, commercial) | C9 |
| ऑपरेटिंग तापमान | 0°C to +85°C | 0 C to +85 C (commercial) |
| RoHS स्थिति | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Lead Free | Yes | — |
| Process Technology | 0.15 µm CMOS | 0.18 um CMOS |
| Typical Gate Count | — | 1,000,000 system gates |
| Logic Elements | — | 38,400 |
| Logic Array Blocks (LABs) | — | 3,840 |
| Embedded System Blocks (ESBs) | — | 212 |
| Total Embedded RAM Bits | — | 327,680 bits |
| Maximum User I/O Pins | — | 708 |
| पैकेज | — | 1,020-ball FineLine BGA (FBGA) |
| Logic Element Architecture | — | 4-input LUT with dedicated carry chain |
| Maximum Embedded RAM per ESB | — | 32,768 bits (dual-port, FIFO support) |
| Phase-Locked Loops | — | Up to 4 enhanced PLLs |
| MultiVolt I/O Support | — | 1.8V / 2.5V / 3.3V / 5.0V |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Configuration Method | — | Passive serial / Passive parallel / JTAG |
| Lead-Free | — | [DATA_NEEDED: lead-free finish status] |