EP20K1500CF33C8 vs EP20K1500CF33C8ES तुलना
विस्तृत दोनों ओर की तुलना EP20K1500CF33C8 द्वारा Altera और EP20K1500CF33C8ES द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP20K1500CF33C8 | EP20K1500CF33C8ES |
|---|---|---|
| ब्रांड | Altera | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | अंतिम बार खरीदें |
| Family | APEX 20K | — |
| Logic Elements / Cells | 51,840 | — |
| Total RAM Bits | 442,368 | — |
| Number of Gates (typical) | 1,500,000 | — |
| Number of I/O | 808 (maximum user I/O) | — |
| Number of LABs/CLBs | 2,592 LABs (organized in MegaLABs) | — |
| Number of Embedded System Blocks | 216 ESBs | — |
| Number of PLLs | 4 | 4 |
| Supply Voltage (VCCINT) | 1.8 V (typical for APEX 20K core) | — |
| Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) | — |
| ऑपरेटिंग तापमान | 0 °C to +85 °C (Commercial) | [DATA_NEEDED: operating temperature range] |
| माउंटिंग प्रकार | Surface Mount (BGA) | Surface Mount |
| पैकेज / केस | 1020-BBGA, FCBGA (FineLine BGA) | — |
| Number of Terminals | 1020 balls | — |
| Process Technology | 0.18 µm CMOS, SRAM-based configuration | — |
| Configuration | SRAM-based, JTAG (IEEE 1149.1) | — |
| RoHS स्थिति | Compliant per distributor listings | [DATA_NEEDED: RoHS compliance for ES variant] |
| Lead-Free | Yes (per distributor specifications) | [DATA_NEEDED: lead-free status] |
| Series | — | APEX 20K (APEX 20KE family) |
| Manufacturer | — | Intel (formerly Altera) |
| System Gates | — | 1,500,000 |
| Maximum Gates (Equivalent) | — | 2,392,000 |
| Logic Elements | — | 51,840 |
| Embedded System Block (ESB) Bits | — | 442,368 |
| CAM Bits | — | 216 Kbit |
| Number of Clocks | — | 8 clock pins |
| Maximum User I/O | — | 808 (1020-FBGA) |
| पैकेज | — | 1020-FBGA (FCBGA), 33x33 mm |
| Speed Grade | — | -1 (C8) |
| Voltage - Supply (Core) | — | 1.8 V nominal (multiVolt I/O supports 1.8/2.5/3.3/5.0 V) |
| I/O Standard Support | — | LVTTL, LVCMOS, PCI, SSTL, HSTL, LVDS (multiVolt) |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| Programming Interface | — | ByteBlaster / MasterBlaster / Altera USB-Blaster |
| Sample Tier | — | ES (engineering sample) |