EP20K1500CF33C8 vs EP20K1500CF33C8ES Karşılaştırma
Ayrıntılı yan yana karşılaştırma EP20K1500CF33C8 tarafından Altera ve EP20K1500CF33C8ES tarafından IntelAnahtar özellikleri, elektriksel parametreleri, ambalajı, yaşam döngüsü durumu, fiyatlandırma ve mevcudiyeti karşılaştırarak tasarım gereksinimleriniz için en iyi bileşeni belirleyin.
Özellik Karşılaştırması
| Parametre | EP20K1500CF33C8 | EP20K1500CF33C8ES |
|---|---|---|
| Marka | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Yaşam Döngüsü Durumu | Obsolete | Son Alış Zamanı |
| Family | APEX 20K | — |
| Logic Elements / Cells | 51,840 | — |
| Total RAM Bits | 442,368 | — |
| Number of Gates (typical) | 1,500,000 | — |
| Number of I/O | 808 (maximum user I/O) | — |
| Number of LABs/CLBs | 2,592 LABs (organized in MegaLABs) | — |
| Number of Embedded System Blocks | 216 ESBs | — |
| Number of PLLs | 4 | 4 |
| Supply Voltage (VCCINT) | 1.8 V (typical for APEX 20K core) | — |
| Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) | — |
| İşletim Sıcaklığı | 0 °C to +85 °C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Montaj Türü | Surface Mount (BGA) | Surface Mount |
| Paket / Kas | 1020-BBGA, FCBGA (FineLine BGA) | — |
| Number of Terminals | 1020 balls | — |
| Process Technology | 0.18 µm CMOS, SRAM-based configuration | — |
| Configuration | SRAM-based, JTAG (IEEE 1149.1) | — |
| RoHS Durumu | Compliant per distributor listings | [DATA_NEEDED: RoHS compliance for ES variant] |
| Lead-Free | Yes (per distributor specifications) | [DATA_NEEDED: lead-free status] |
| Series | — | APEX 20K (APEX 20KE family) |
| Manufacturer | — | Intel (formerly Altera) |
| System Gates | — | 1,500,000 |
| Maximum Gates (Equivalent) | — | 2,392,000 |
| Logic Elements | — | 51,840 |
| Embedded System Block (ESB) Bits | — | 442,368 |
| CAM Bits | — | 216 Kbit |
| Number of Clocks | — | 8 clock pins |
| Maximum User I/O | — | 808 (1020-FBGA) |
| Paket | — | 1020-FBGA (FCBGA), 33x33 mm |
| Speed Grade | — | -1 (C8) |
| Voltage - Supply (Core) | — | 1.8 V nominal (multiVolt I/O supports 1.8/2.5/3.3/5.0 V) |
| I/O Standard Support | — | LVTTL, LVCMOS, PCI, SSTL, HSTL, LVDS (multiVolt) |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| Programming Interface | — | ByteBlaster / MasterBlaster / Altera USB-Blaster |
| Sample Tier | — | ES (engineering sample) |