EP20K400CF672C8ES vs EP20K400CF672C-8 तुलना
विस्तृत दोनों ओर की तुलना EP20K400CF672C8ES द्वारा Altera और EP20K400CF672C-8 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP20K400CF672C8ES | EP20K400CF672C-8 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20K |
| Series | EP20K400 | — |
| Logic Cells / Macros | 16,640 | — |
| System Gates (typical) | 400,000 | — |
| System Gates (maximum) | 212,992 [DATA_NEEDED: confirm datasheet interpretation] | — |
| Maximum User I/O | 488 (per Globalspec) / 484 (per Microchip USA) [DATA_NEEDED: confirm canonical value] | 488 |
| Bidirectional I/O | 484 | — |
| Propagation Delay | 2.5 ns | — |
| Maximum Internal Frequency | 301.21 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm all-layer copper CMOS |
| Nominal Supply Voltage | 1.8 V | — |
| Supply Voltage Range | 1.71 V to 1.89 V | — |
| ऑपरेटिंग तापमान | 0°C to 85°C (Commercial) | — |
| पैकेज | 672-BGA FineLine (FC-FBGA / S-PBGA-B672) | — |
| Logic Family | CMOS | — |
| Architecture | MultiCore™ (LUT + Embedded System Block) | — |
| Programming Method | JTAG / in-system via configuration memory | — |
| RoHS स्थिति | [DATA_NEEDED: not stated in verified data] | [DATA_NEEDED: RoHS compliance] |
| Logic Elements | — | 16,640 |
| Typical Gates | — | 400,000 |
| Macros | — | 1,664 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Package Type | — | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) |
| Core Voltage (VCCINT) | — | 1.8 V nominal (1.71 V to 1.89 V) |
| I/O Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO options] |
| Pin-to-Pin Delay (tPD) | — | 1.78 ns (speed grade -8) |
| Speed Grade | — | -8 |
| Temperature Grade (C) | — | Commercial, 0 °C to 85 °C |
| Embedded Memory Type | — | ESB (RAM / ROM / CAM) |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| माउंटिंग प्रकार | — | Surface Mount (BGA) |
| MSL स्तर | — | [DATA_NEEDED: MSL level] |