EP2A25F672I-9 vs EP2A25F672I9N तुलना
विस्तृत दोनों ओर की तुलना EP2A25F672I-9 द्वारा Intel और EP2A25F672I9N द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP2A25F672I-9 | EP2A25F672I9N |
|---|---|---|
| ब्रांड | Intel | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | APEX II | APEX II |
| Logic Elements (typical) | 25,000 | — |
| Maximum System Gates | [DATA_NEEDED: maximum system gates] | — |
| Embedded System Blocks (ESB) Memory | 1,125 Kbits | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O pins] | — |
| Number of PLLs | 4 | — |
| Process Technology | 0.18 µm CMOS | 0.15 µm CMOS |
| Core Voltage | 1.5 V / 1.8 V (speed-grade dependent) | — |
| Operating Temperature Grade | Industrial (-40 °C to +100 °C junction) | — |
| Speed Grade | -9 | 9 (fastest commercial APEX II) |
| पैकेज | 672-pin FCBGA (FineLine BGA) | 672-pin FC-FBGA |
| माउंटिंग प्रकार | Surface Mount (BGA) | Surface Mount |
| नमी संवेदनशीलता स्तर (MSL) | 3 (per Vyrian listing) | — |
| Peak Reflow Temperature | 220 °C (per Vyrian listing) | — |
| Configuration Method | JTAG / serial configuration EPROM | — |
| Supported I/O Standards | LVTTL, LVCMOS, LVDS, PCI | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirmed] |
| Legacy Status | Obsolete - consult Altera / Intel FPGA archive for documentation | — |
| Series | — | APEX II (EP2A25) |
| Device Type | — | FPGA (Field-Programmable Gate Array) |
| Logic Elements / Cells | — | 24,320 |
| System Gates | — | 900,000 (typical) |
| Maximum Internal Frequency | — | 236 MHz |
| Propagation Delay (tpd) | — | 2.23 ns |
| Core Supply Voltage (VCCINT) | — | 1.5 V nominal (1.425 V to 1.525 V) |
| I/O Supply Voltage | — | [DATA_NEEDED: VCCIO range] |
| ऑपरेटिंग तापमान | — | -40 °C to +85 °C (Industrial, 'I' suffix) |
| Embedded System Blocks (ESB) | — | Yes (on-chip RAM/ROM) |
| PLLs | — | 4 |
| Configuration | — | JTAG / in-system programmable |
| MSL स्तर | — | [DATA_NEEDED] |
| AEC-Q100 | — | not_applicable |