EP2A25F672I-9 vs EP2A25F672I9N 比較
詳細並排比較 EP2A25F672I-9 由 Intel 與 EP2A25F672I9N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2A25F672I-9 | EP2A25F672I9N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX II | APEX II |
| Logic Elements (typical) | 25,000 | — |
| Maximum System Gates | [DATA_NEEDED: maximum system gates] | — |
| Embedded System Blocks (ESB) Memory | 1,125 Kbits | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O pins] | — |
| Number of PLLs | 4 | — |
| Process Technology | 0.18 µm CMOS | 0.15 µm CMOS |
| Core Voltage | 1.5 V / 1.8 V (speed-grade dependent) | — |
| Operating Temperature Grade | Industrial (-40 °C to +100 °C junction) | — |
| Speed Grade | -9 | 9 (fastest commercial APEX II) |
| 封裝 | 672-pin FCBGA (FineLine BGA) | 672-pin FC-FBGA |
| 安裝類型 | Surface Mount (BGA) | Surface Mount |
| 濕度敏感等級 (MSL) | 3 (per Vyrian listing) | — |
| Peak Reflow Temperature | 220 °C (per Vyrian listing) | — |
| Configuration Method | JTAG / serial configuration EPROM | — |
| Supported I/O Standards | LVTTL, LVCMOS, LVDS, PCI | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirmed] |
| Legacy Status | Obsolete - consult Altera / Intel FPGA archive for documentation | — |
| Series | — | APEX II (EP2A25) |
| Device Type | — | FPGA (Field-Programmable Gate Array) |
| Logic Elements / Cells | — | 24,320 |
| System Gates | — | 900,000 (typical) |
| Maximum Internal Frequency | — | 236 MHz |
| Propagation Delay (tpd) | — | 2.23 ns |
| Core Supply Voltage (VCCINT) | — | 1.5 V nominal (1.425 V to 1.525 V) |
| I/O Supply Voltage | — | [DATA_NEEDED: VCCIO range] |
| 工作溫度 | — | -40 °C to +85 °C (Industrial, 'I' suffix) |
| Embedded System Blocks (ESB) | — | Yes (on-chip RAM/ROM) |
| PLLs | — | 4 |
| Configuration | — | JTAG / in-system programmable |
| MSL 等級 | — | [DATA_NEEDED] |
| AEC-Q100 | — | not_applicable |