EPC81500RC304-3 vs EPC16UC88 तुलना
विस्तृत दोनों ओर की तुलना EPC81500RC304-3 द्वारा Altera और EPC16UC88 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Altera
EPC81500RC304-3 - Enhanced Configuration Device for SRAM FPGAs | Altera
EPC81500RC304-3 Obsolete
विशेषता तुलना
| पैरामीटर | EPC81500RC304-3 | EPC16UC88 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | Memory ICs |
| लाइफसाइकिल स्थिति | Obsolete | Unknown |
| Device Type | Enhanced Configuration Device (Flash-based FPGA configuration memory) | In-system programmable configuration PROM for FPGAs |
| Target FPGA Families | Altera FLEX 8000, FLEX 10K, ACEX 1K, APEX series SRAM-based LUT FPGAs | — |
| Configuration Memory Size | 8 Mbit | — |
| Interface Modes | Parallel-byte and serial bitstream modes | — |
| Programming Interface | JTAG (IEEE 1149.1) and byte-wide parallel | — |
| Supply Voltage VCCINT | 3.3 V | — |
| I/O Voltage VCCIO | 3.3 V or 5.0 V tolerant | — |
| ऑपरेटिंग तापमान रेंज | 0 C to +70 C (commercial) | — |
| पैकेज | 304-pin PQFP (RC304) | 88-UBGA (11x8) |
| माउंटिंग प्रकार | Surface Mount | Surface mount |
| पिन काउंट | 304 | — |
| Configuration Clock | DCLK generated internally or externally to target FPGA | — |
| Multi-Device Support | Yes - daisy-chain configuration of multiple FPGAs | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Configuration Memory Capacity | — | 16 Mb |
| सप्लाई वोल्टेज | — | 3.3 V core and I/O |
| Package Family | — | UBGA |
| In-System Programmability | — | IEEE Std. 1532 compatible |
| Programming Language Support | — | Jam Standard Test and Programming Language (STAPL) |
| JTAG Boundary Scan | — | Supported |
| nINIT_CONF Function | — | Allows private JTAG instruction to start FPGA configuration |
| Configuration Architecture | — | Configuration controller and flash memory |
| FPGA Configuration Use | — | Automatic configuration after power-up or system initialization |
| Data Output | — | Configuration data output controlled by OE and nCS |
| Output Control | — | OE and nCS control tri-state buffer and address counter |
| Package Dimensions | — | 11 mm x 8 mm |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| ऑपरेटिंग तापमान | — | [DATA_NEEDED: operating temperature] |
| Output Current | — | [DATA_NEEDED: output current] |
| Configuration Frequency | — | [DATA_NEEDED: configuration frequency] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |