EPF8820ARC208-5 vs EPF8820ARC208-3 तुलना
विस्तृत दोनों ओर की तुलना EPF8820ARC208-5 द्वारा Altera और EPF8820ARC208-3 द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Altera
EPF8820ARC208-5 - FLEX 8000 FPGA, 672 Logic Elements, 152 I/O | Altera
EPF8820ARC208-5 ObsoleteIntel
EPF8820ARC208-3 - FLEX 8000 FPGA, 8K Gates, 672 Cells | Intel / Altera
EPF8820ARC208-3 Obsoleteविशेषता तुलना
| पैरामीटर | EPF8820ARC208-5 | EPF8820ARC208-3 |
|---|---|---|
| ब्रांड | Altera | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | FLEX 8000 | FLEX 8000 (EPF8820) |
| Logic Elements | 672 | — |
| Number of I/O Pins | 152 | — |
| Number of Logic Gates | [DATA_NEEDED: gate count] | — |
| Speed Grade | -5 (slowest) | — |
| Supply Voltage (Core) | 4.75V to 5.25V (5.0V nominal) | — |
| I/O Voltage | 3.3V or 5.0V (MultiVolt) | — |
| Configuration Method | CMOS SRAM (volatile, loaded at power-up) | — |
| पैकेज | 208-BFQFP Exposed Pad (28x28 mm) | — |
| पिन काउंट | 208 | — |
| ऑपरेटिंग तापमान | [DATA_NEEDED: temperature grade] | — |
| माउंटिंग प्रकार | Surface Mount | Surface Mount |
| MSL स्तर | [DATA_NEEDED: MSL rating] | — |
| RoHS स्थिति | unknown | [DATA_NEEDED: RoHS status] |
| Lead-Free | unknown | — |
| Process Technology | CMOS SRAM | 0.42 µm CMOS |
| Dedicated Inputs | [DATA_NEEDED: dedicated input count] | — |
| Series | — | FLEX 8000 |
| Usable Gates | — | 8,000 |
| Logic Cells / Elements | — | 672 |
| Registers | — | 152 |
| Maximum Operating Frequency | — | 125 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Configuration Memory | — | SRAM (volatile) |
| पैकेज / केस | — | 208-BFQFP Exposed Pad (208-RQFP, 28x28 mm) |
| Supplier Device Package | — | 208-RQFP (28x28) |
| Packaging | — | Tray |
| ऑपरेटिंग तापमान रेंज | — | [DATA_NEEDED: operating temperature range] |
| In-Circuit Reconfigurability (ICR) | — | Yes (via external configuration devices) |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |
| I/O Tolerance | — | 3.3 V / 5 V |
| Clock Networks | — | 4 dedicated low-skew global clocks |
| Lead-Free / Finish | — | [DATA_NEEDED: lead-free finish] |