EPM3064ATI44-10N vs EPM3064ALC44-10N तुलना
विस्तृत दोनों ओर की तुलना EPM3064ATI44-10N द्वारा Altera और EPM3064ALC44-10N द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Altera
EPM3064ALC44-10N - MAX 3000A CPLD, 64 Macrocells, 34 I/O | Intel / Altera
EPM3064ALC44-10N Obsoleteविशेषता तुलना
| पैरामीटर | EPM3064ATI44-10N | EPM3064ALC44-10N |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | MAX 3000A | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 64 | 64 |
| Usable Gates | 1250 | 1,250 |
| User I/Os | 34 | — |
| Dedicated Inputs | 4 | — |
| Logic Blocks | 4 | — |
| Pin-to-Pin Delay | 10 ns (-10 speed grade) | — |
| Maximum Frequency (fMAX) | 100 MHz | — |
| Programmable Type | In-System Programmable (EEPROM) | — |
| ISP Interface | IEEE Std. 1149.1 (JTAG) | — |
| ISP Standard Compliance | IEEE Std. 1532 | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V (MultiVolt) | — |
| ऑपरेटिंग तापमान | -40C to +85C (Industrial, "N" suffix) | [DATA_NEEDED: commercial / industrial grade] |
| पैकेज | 44-pin TQFP | 44-pin PLCC (LC44) |
| Process Technology | CMOS EEPROM | — |
| Boundary-Scan Test | Built-in (JTAG) | — |
| माउंटिंग प्रकार | Surface Mount | Surface Mount (PLCC socket compatible) |
| Lead-Free Status | Contains Lead (per digchip datasheet excerpt) | — |
| RoHS स्थिति | Non-Compliant (per digchip datasheet excerpt) | Compliant |
| Product Family | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 4 |
| User I/O Pins | — | 34 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| I/O Bank Voltage (VCCIO) | — | 3.0 V to 3.6 V (MultiVolt) |
| Configuration Memory | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant) |
| Open-Drain Output Option | — | Yes (per I/O pin) |
| Output Slew-Rate Control | — | Programmable |