EPM5192AJC84-15 vs EPM5192AJC-15 तुलना
विस्तृत दोनों ओर की तुलना EPM5192AJC84-15 द्वारा Altera और EPM5192AJC-15 द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Altera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 Obsoleteविशेषता तुलना
| पैरामीटर | EPM5192AJC84-15 | EPM5192AJC-15 |
|---|---|---|
| ब्रांड | Altera | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | NRND |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 15 ns | — |
| Maximum Clock Frequency (fMAX) | 83.3 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS, UV-erasable EPROM | — |
| पैकेज | 84-pin PLCC (J84C) windowed ceramic | 84-pin PLCC (J-lead, ceramic, non-windowed) |
| माउंटिंग प्रकार | Surface Mount | Surface Mount |
| ऑपरेटिंग तापमान | [DATA_NEEDED: commercial/industrial/military grade] | 0C to +70C (commercial) |
| Programming Method | UV-erase + EPROM programming (windowed package) | — |
| Logic Blocks | 16 Logic Array Blocks (LABs) | — |
| I/O Pins | [DATA_NEEDED: user I/O count] | — |
| RoHS स्थिति | Non-compliant (contains Pb, ceramic windowed package) | [DATA_NEEDED: RoHS compliance] |
| Process Technology | CMOS EPROM | — |
| Logic Capacity | — | 100% connectivity, sum-of-products PLA architecture |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Programmability | — | UV-erasable (windowed variant) / One-Time-Programmable |
| Toolchain | — | MAX+PLUS II |
| पिन काउंट | — | 84 |
| User I/O Pins | — | [DATA_NEEDED: user I/O count] |
| Speed Grades Available | — | -15, -20, -25 (this part: -15) |
| Configuration Memory | — | EPROM (UV-erasable) |