EPM9320RI208-20C vs EPM9320RC208-20 तुलना
विस्तृत दोनों ओर की तुलना EPM9320RI208-20C द्वारा Altera और EPM9320RC208-20 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Altera
EPM9320RI208-20C - 320-Macrocell MAX 9000 CPLD, 5V, 208-RQFP | Intel
EPM9320RI208-20C Obsoleteविशेषता तुलना
| पैरामीटर | EPM9320RI208-20C | EPM9320RC208-20 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE PLD / CPLD | CPLD (Complex Programmable Logic Device) |
| Logic Elements / Macrocells | 320 | — |
| Usable Gates | 6,000 | 6,000 |
| Number of Flip-Flops | 484 | — |
| Logic Array Blocks (LABs) | 16 | 20 |
| Maximum Internal Clock Frequency | 100 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 20 ns | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| I/O Voltage Tolerance | 3.3 V or 5.0 V | — |
| Programmable Interface | JTAG (IEEE Std. 1149.1) BST | — |
| In-System Programmability | Yes (5.0 V ISP via JTAG) | — |
| Technology | CMOS EEPROM | — |
| पैकेज | 208-pin RQFP (Plastic Quad Flat Pack) | 208-RQFP, exposed pad (208-BFQFP) |
| Operating Temperature (Industrial) | -40C to +85C | — |
| माउंटिंग प्रकार | Surface Mount | Surface Mount |
| Lead-Free / RoHS | Information not confirmed from verified data [DATA_NEEDED: RoHS status] | — |
| Macrocells | — | 320 |
| Maximum I/O Pins | — | 132 |
| Propagation Delay (tPD max) | — | 20 ns |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V |
| Programming Technology | — | EEPROM, in-system programmable (ISP) |
| Boundary-Scan Interface | — | IEEE Std. 1149.1 (JTAG) |
| ऑपरेटिंग तापमान | — | 0 °C to 70 °C (commercial) |
| Architecture | — | Multiple Array Matrix (MAX), 3rd generation |
| Process Technology | — | CMOS, 5.0 V EEPROM |
| Reprogrammability | — | Yes, unlimited ISP cycles |