EPM9560GC280-20 vs EPM9560GI280-20 तुलना
विस्तृत दोनों ओर की तुलना EPM9560GC280-20 द्वारा Altera और EPM9560GI280-20 द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EPM9560GC280-20 | EPM9560GI280-20 |
|---|---|---|
| ब्रांड | Altera | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | NRND |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| Maximum User I/O | 212 | — |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| Counter Frequency (max) | 100 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| I/O Voltage | 3.3 V or 5.0 V configurable | — |
| Process Technology | CMOS EEPROM | — |
| पैकेज | 280-pin CPGA (Ceramic Pin Grid Array) | 280-pin PGA (PIN/PEG, square) |
| ऑपरेटिंग तापमान | [DATA_NEEDED: commercial/industrial/military grade] | — |
| In-System Programming | Yes, via IEEE 1149.1 JTAG | — |
| माउंटिंग प्रकार | Through-Hole (CPGA socket) | — |
| RoHS स्थिति | [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] | [DATA_NEEDED: RoHS status for GI PGA package] |
| Device Family | — | MAX 9000 |
| Architecture | — | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Technology Node | — | 5.0 V CMOS EEPROM |
| Logic Array Blocks (LABs) | — | 28 (16 macrocells each) |
| Maximum User I/O Pins | — | 216 |
| Flip-Flops | — | 772 |
| Pin-to-Pin Delay (Speed Grade) | — | 20 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG) |
| Programming Technology | — | EEPROM (non-volatile) |
| Terminal Form | — | PIN/PEG (through-hole PGA) |
| Package Code | — | PGA |
| Temperature Grade | — | Industrial |
| I/O Pin DC Input Range | — | -0.5 V to VCC + 0.5 V |
| Dedicated-Input Pin DC Input Range | — | -0.3 V to VCC + 0.3 V |
| I/O Transient Envelope (no-load, <20 ns) | — | -2.0 V undershoot to 7.0 V overshoot |
| VCC Ramp Requirement | — | Monotonic rise |
| Development Tool | — | Altera MAX+PLUS II |
| Supported HDLs | — | VHDL, Verilog HDL, AHDL |