RTAX2000S-1CGS624V vs RTAX2000S-CGS624V तुलना
विस्तृत दोनों ओर की तुलना RTAX2000S-1CGS624V द्वारा Microchip Technology और RTAX2000S-CGS624V द्वारा Microchip Technology. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Microchip Technology
RTAX2000S-1CGS624V - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000S-1CGS624V ✓ सक्रियMicrochip Technology
RTAX2000S-CGS624V - 2M-Gate Rad-Tolerant FPGA CG624 | Microchip
RTAX2000S-CGS624V ✓ सक्रियविशेषता तुलना
| पैरामीटर | RTAX2000S-1CGS624V | RTAX2000S-CGS624V |
|---|---|---|
| ब्रांड | Microchip Technology | Microchip Technology |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | सक्रिय | सक्रिय |
| Family | RTAX-S Radiation-Tolerant FPGA | RTAX-S/SL Radiation-Tolerant FPGA |
| Equivalent System Gates | 2,000,000 | 2000000 |
| Configurable Logic Blocks (CLBs) | 21,504 | 21504 |
| Total Logic Cells | 32,256 | — |
| ASIC Gate Capacity (companion) | 250,000 gates | — |
| Core Supply Voltage (nominal) | 1.5 V | — |
| Core Supply Voltage Range | 1.425 V to 1.575 V | 1.425 V to 1.575 V |
| Logic Family | CMOS | — |
| Speed Grade | -1 | — |
| ऑपरेटिंग तापमान | -55C to +125C | -55C to +125C |
| पैकेज | CG624 Ceramic Column Grid Array (CCGA), 624 balls | CG624 ceramic column grid array |
| माउंटिंग प्रकार | Surface Mount | Surface Mount |
| Programming Technology | Antifuse (one-time programmable) | — |
| SEU Hardening | SEU-hardened registers, immune to single-event upsets | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| Configuration | Live at power-up, single-chip (no external config device) | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS status] | — |
| Weight | [DATA_NEEDED: package weight] | — |
| Logic Cells | — | 32256 |
| Technology | — | Digital CMOS, anti-fuse OTP |
| Core Supply Voltage (Nominal) | — | 1.5 V |
| Configuration Type | — | One-Time Programmable (anti-fuse), live at power-up |
| Clocking | — | Segmentable clocks |
| Routing Features | — | Chip-wide highway routing, carry logic |
| Application Domain | — | Space-flight systems |
| Max Family Density | — | 4000000 equivalent system gates (family max) |