RTAX2000SL-1CGS624B vs RTAX2000S-1CGS624EV तुलना
विस्तृत दोनों ओर की तुलना RTAX2000SL-1CGS624B द्वारा Microchip Technology और RTAX2000S-1CGS624EV द्वारा Microchip Technology. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Microchip Technology
RTAX2000SL-1CGS624B - Rad-Tolerant FPGA 2M Gates CCGA624 | Microchip
RTAX2000SL-1CGS624B ✓ सक्रियMicrochip Technology
RTAX2000S-1CGS624EV - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000S-1CGS624EV ✓ सक्रियविशेषता तुलना
| पैरामीटर | RTAX2000SL-1CGS624B | RTAX2000S-1CGS624EV |
|---|---|---|
| ब्रांड | Microchip Technology | Microchip Technology |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | सक्रिय | सक्रिय |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | — |
| Logic Blocks (CLBs) | 21504 | — |
| Equivalent System Gates | 2000000 | — |
| ASIC Gates | 250000 | — |
| Process Technology | 0.15 um CMOS | 0.15 um CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V nominal (1.425 V to 1.575 V) |
| Speed Grade | -1 | — |
| अधिकतम क्लॉक फ़्रीक्वेंसी | 649 MHz (family max, Jotrin listing) | — |
| Programmability | One-Time Programmable (antifuse) | — |
| Configuration | Live at power-up, single-chip | One-time programmable anti-fuse, live at power-up, single chip |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| Radiation Tolerance | Radiation-tolerant (space-flight qualified family) | — |
| पैकेज | 624-pin Ceramic Column Grid Array (CCGA / CGA-624, ceramic) | 624-pin Ceramic Column Grid Array (CGA-624 / CCGA624) |
| माउंटिंग प्रकार | Surface Mount | Surface Mount |
| ऑपरेटिंग तापमान | [DATA_NEEDED: operating temperature range] | -55C to +125C |
| I/O Count | [DATA_NEEDED: user I/O count] | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| System Gates | — | 2,000,000 |
| Logic Cells (CLBs) | — | 21504 |
| Total Cells | — | 32256 |
| Additional ASIC Equivalent Gates | — | 250000 |
| Maximum Frequency | — | 649 MHz |
| Logic Family | — | CMOS |
| SEU Immunity | — | SEU-hardened registers, immune to single-event upsets to specified LET threshold |
| SEU Rate | — | < 10-10 errors/bit-day |
| Product Family | — | RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs |
| Thermal Resistance Basis | — | JEDEC JESD51 simulation conditions (per datasheet) |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O bank voltage] |
| Maximum User I/O | — | [DATA_NEEDED: user I/O count] |